Initial commit

2026-04-23 17:07:55 +08:00
commit b7e39e063b
16725 changed files with 1625565 additions and 0 deletions
@@ -0,0 +1,4 @@
+Arm platforms BSPs
+==================
+
+This directory contains Arm platforms definitions and configuration for Linux.
@@ -0,0 +1,17 @@
+# SPDX-License-Identifier: MIT
+#
+# ARM64
+#
+CONFIG_ARM64=y
+CONFIG_64BIT=y
+CONFIG_ARCH_VEXPRESS=y
+
+#
+# Bus support
+#
+CONFIG_ARM_AMBA=y
+
+#
+# Bus devices
+#
+CONFIG_VEXPRESS_CONFIG=y
@@ -0,0 +1,5 @@
+define KMACHINE corstone1000
+define KTYPE standard
+define KARCH arm64
+
+kconf hardware corstone1000/base.cfg
@@ -0,0 +1,29 @@
+CONFIG_LOCALVERSION="-yocto-standard"
+# CONFIG_LOCALVERSION_AUTO is not set
+CONFIG_LOG_BUF_SHIFT=12
+# CONFIG_UTS_NS is not set
+# CONFIG_PID_NS is not set
+# CONFIG_NET_NS is not set
+# CONFIG_BLK_DEV_BSG is not set
+CONFIG_ARM64=y
+CONFIG_THUMB2_KERNEL=y
+CONFIG_ZBOOT_ROM_TEXT=0x0
+CONFIG_ZBOOT_ROM_BSS=0x0
+CONFIG_VFP=y
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+CONFIG_NET=y
+CONFIG_PACKET=y
+CONFIG_UNIX=y
+CONFIG_INET=y
+# CONFIG_IPV6 is not set
+# CONFIG_WIRELESS is not set
+CONFIG_DEVTMPFS=y
+CONFIG_TMPFS=y
+# CONFIG_WLAN is not set
+# CONFIG_SERIO_SERPORT is not set
+CONFIG_SERIAL_AMBA_PL011=y
+CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_DRV_PL031=y
+CONFIG_MAILBOX=y
+# CONFIG_CRYPTO_HW is not set
@@ -0,0 +1,6 @@
+define KMACHINE fvp-baser-aemv8r64
+define KTYPE preempt-rt
+define KARCH arm64
+
+include ktypes/preempt-rt/preempt-rt.scc
+include fvp-baser-aemv8r64.scc
@@ -0,0 +1,7 @@
+define KMACHINE fvp-baser-aemv8r64
+define KTYPE standard
+define KARCH arm64
+
+include ktypes/standard/standard.scc
+
+include fvp-baser-aemv8r64.scc
@@ -0,0 +1,4 @@
+kconf hardware arm64.cfg
+kconf hardware fvp-common-peripherals.cfg
+include cfg/virtio.scc
+include virtio-9p.scc
@@ -0,0 +1,8 @@
+# SPDX-License-Identifier: MIT
+CONFIG_SERIAL_AMBA_PL011=y
+CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
+
+CONFIG_ARM_SP805_WATCHDOG=y
+
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_DRV_PL031=y
@@ -0,0 +1,11 @@
+define KMACHINE fvp
+define KTYPE standard
+define KARCH arm64
+
+include ktypes/standard/standard.scc
+
+include fvp.scc
+
+# default policy for standard kernels
+#include features/latencytop/latencytop.scc
+#include features/profiling/profiling.scc
@@ -0,0 +1,13 @@
+include features/input/input.scc
+include features/net/net.scc
+include cfg/timer/no_hz.scc
+include cfg/virtio.scc
+
+kconf hardware fvp/fvp-board.cfg
+kconf hardware fvp/fvp-net.cfg
+kconf hardware fvp/fvp-rtc.cfg
+kconf hardware fvp/fvp-serial.cfg
+kconf hardware fvp/fvp-cfi.cfg
+kconf hardware fvp/fvp-drm.cfg
+kconf hardware fvp/fvp-timer.cfg
+kconf hardware fvp/fvp-watchdog.cfg
@@ -0,0 +1,10 @@
+CONFIG_ARM64=y
+CONFIG_ARCH_VEXPRESS=y
+CONFIG_SMP=y
+CONFIG_NR_CPUS=8
+CONFIG_HOTPLUG_CPU=y
+
+CONFIG_REGULATOR=y
+CONFIG_REGULATOR_FIXED_VOLTAGE=y
+
+CONFIG_CPU_IDLE=y
@@ -0,0 +1,3 @@
+# CFI Flash
+CONFIG_MTD=y
+CONFIG_MTD_CFI=y
@@ -0,0 +1,5 @@
+# DRM CLCD
+CONFIG_DRM=y
+CONFIG_DRM_PL111=y
+CONFIG_FB=y
+CONFIG_FB_ARMCLCD=y
@@ -0,0 +1,3 @@
+CONFIG_NET_VENDOR_SMSC=y
+CONFIG_SMSC911X=y
+CONFIG_SMC91X=y
@@ -0,0 +1,2 @@
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_DRV_PL031=y
@@ -0,0 +1,2 @@
+CONFIG_SERIAL_AMBA_PL011=y
+CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
@@ -0,0 +1,4 @@
+# Dual timer module
+CONFIG_COMPILE_TEST=y
+CONFIG_ARM_TIMER_SP804=y
+CONFIG_CLK_SP810=y
@@ -0,0 +1,3 @@
+# Watchdog
+CONFIG_WATCHDOG=y
+CONFIG_ARM_SP805_WATCHDOG=y
@@ -0,0 +1,11 @@
+define KMACHINE juno
+define KTYPE standard
+define KARCH arm64
+
+include ktypes/standard/standard.scc
+
+include juno.scc
+
+# default policy for standard kernels
+#include features/latencytop/latencytop.scc
+#include features/profiling/profiling.scc
@@ -0,0 +1,24 @@
+include features/input/input.scc
+include features/net/net.scc
+include features/usb/usb-base.scc
+include features/bluetooth/bluetooth.scc
+include cfg/timer/no_hz.scc
+include cfg/usb-mass-storage.scc
+
+kconf hardware juno/juno-board.cfg
+kconf hardware juno/juno-devfreq.cfg
+kconf hardware juno/juno-dma.cfg
+kconf hardware juno/juno-drm.cfg
+kconf hardware juno/juno-fb.cfg
+kconf hardware juno/juno-i2c.cfg
+# kconf hardware juno/juno-mali-midgard.cfg
+kconf hardware juno/juno-mmc.cfg
+kconf hardware juno/juno-net.cfg
+kconf hardware juno/juno-pci.cfg
+kconf hardware juno/juno-rtc.cfg
+kconf hardware juno/juno-sata.cfg
+kconf hardware juno/juno-serial.cfg
+kconf hardware juno/juno-sound.cfg
+kconf hardware juno/juno-thermal.cfg
+kconf hardware juno/juno-usb.cfg
+
@@ -0,0 +1,42 @@
+CONFIG_ARM64=y
+CONFIG_ARCH_VEXPRESS=y
+CONFIG_SMP=y
+CONFIG_NR_CPUS=8
+CONFIG_HOTPLUG_CPU=y
+
+# Keyboard over AMBA
+CONFIG_SERIO=y
+CONFIG_SERIO_AMBAKMI=y
+
+# Hardware mailbox
+CONFIG_MAILBOX=y
+CONFIG_ARM_MHU=y
+
+# SCMI support
+CONFIG_HWMON=y
+CONFIG_ARM_SCMI_PROTOCOL=y
+CONFIG_ARM_SCMI_TRANSPORT_MAILBOX=y
+CONFIG_ARM_SCMI_POWER_DOMAIN=y
+CONFIG_SENSORS_ARM_SCMI=y
+CONFIG_COMMON_CLK_SCMI=y
+
+# Power Interface and system control
+CONFIG_ARM_SCPI_PROTOCOL=y
+CONFIG_ARM_SCPI_POWER_DOMAIN=y
+CONFIG_SENSORS_ARM_SCPI=y
+CONFIG_COMMON_CLK_SCPI=y
+
+CONFIG_REGULATOR=y
+CONFIG_REGULATOR_FIXED_VOLTAGE=y
+
+CONFIG_CPU_IDLE=y
+
+CONFIG_CPU_FREQ=y
+CONFIG_ARM_SCPI_CPUFREQ=y
+
+CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
+CONFIG_CPU_FREQ_GOV_USERSPACE=y
+CONFIG_CPU_FREQ_GOV_ONDEMAND=y
+
+CONFIG_CONNECTOR=y
+CONFIG_PRINTK_TIME=y
@@ -0,0 +1,4 @@
+CONFIG_PM_DEVFREQ=y
+CONFIG_DEVFREQ_THERMAL=y
+CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND=y
+CONFIG_DEVFREQ_GOV_PERFORMANCE=y
@@ -0,0 +1,5 @@
+CONFIG_DMADEVICES=y
+CONFIG_PL330_DMA=y
+CONFIG_CMA=y
+CONFIG_DMA_CMA=y
+CONFIG_CMA_SIZE_MBYTES=96
@@ -0,0 +1,5 @@
+CONFIG_DRM=y
+CONFIG_DRM_HDLCD=y
+CONFIG_DRM_I2C_NXP_TDA998X=y
+CONFIG_FB=y
+CONFIG_FB_ARMCLCD=y
@@ -0,0 +1,4 @@
+CONFIG_FB=y
+CONFIG_FB_ARMCLCD=y
+CONFIG_FRAMEBUFFER_CONSOLE=y
+# CONFIG_VGA_CONSOLE is not set
@@ -0,0 +1,2 @@
+CONFIG_I2C=y
+CONFIG_I2C_DESIGNWARE_PLATFORM=y
@@ -0,0 +1,7 @@
+CONFIG_MALI_MIDGARD=y
+CONFIG_MALI_EXPERT=y
+CONFIG_MALI_PLATFORM_FAKE=y
+CONFIG_MALI_PLATFORM_THIRDPARTY=y
+CONFIG_MALI_PLATFORM_THIRDPARTY_NAME="juno_soc"
+CONFIG_MALI_PLATFORM_DEVICETREE=y
+CONFIG_MALI_DEVFREQ=y
@@ -0,0 +1,2 @@
+CONFIG_MMC=y
+CONFIG_MMC_ARMMMCI=y
@@ -0,0 +1,3 @@
+CONFIG_NET_VENDOR_SMSC=y
+CONFIG_SMSC911X=y
+CONFIG_SMC91X=y
@@ -0,0 +1,12 @@
+CONFIG_PCI=y
+CONFIG_PCI_IOV=y
+CONFIG_PCI_MSI=y
+CONFIG_PCI_REALLOC_ENABLE_AUTO=y
+CONFIG_PCI_PRI=y
+CONFIG_PCI_PASID=y
+CONFIG_PCI_HOST_GENERIC=y
+CONFIG_PCIEPORTBUS=y
+CONFIG_HOTPLUG_PCI=y
+CONFIG_HOTPLUG_PCI_PCIE=y
+CONFIG_PCIEAER=y
+CONFIG_PCIE_ECRC=y
@@ -0,0 +1,2 @@
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_DRV_PL031=y
@@ -0,0 +1,2 @@
+CONFIG_ATA=y
+CONFIG_SATA_SIL24=y
@@ -0,0 +1,2 @@
+CONFIG_SERIAL_AMBA_PL011=y
+CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
@@ -0,0 +1,14 @@
+CONFIG_SOUND=y
+CONFIG_SND=y
+CONFIG_SND_SEQUENCER=y
+CONFIG_SND_SEQ_DUMMY=y
+CONFIG_SND_OSSEMUL=y
+CONFIG_SND_MIXER_OSS=y
+CONFIG_SND_PCM_OSS=y
+CONFIG_SND_SEQUENCER_OSS=y
+# CONFIG_SND_USB is not set
+CONFIG_SND_SOC=y
+CONFIG_SND_DESIGNWARE_I2S=y
+CONFIG_SND_SOC_HDMI_CODEC=y
+CONFIG_SND_SOC_SPDIF=y
+CONFIG_SND_SIMPLE_CARD=y
@@ -0,0 +1,8 @@
+CONFIG_THERMAL=y
+CONFIG_THERMAL_OF=y
+CONFIG_ENERGY_MODEL=y
+CONFIG_THERMAL_GOV_POWER_ALLOCATOR=y
+CONFIG_THERMAL_DEFAULT_GOV_POWER_ALLOCATOR=y
+CONFIG_THERMAL_GOV_USER_SPACE=y
+CONFIG_CPU_THERMAL=y
+CONFIG_THERMAL_WRITABLE_TRIPS=y
@@ -0,0 +1,7 @@
+CONFIG_USB_STORAGE=y
+CONFIG_USB=y
+CONFIG_USB_ULPI=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_HCD_PLATFORM=y
+CONFIG_NOP_USB_XCEIV=y
+CONFIG_USB_OHCI_HCD=y
@@ -0,0 +1,6 @@
+define KMACHINE n1sdp
+define KTYPE preempt-rt
+define KARCH arm64
+
+include ktypes/preempt-rt/preempt-rt.scc
+include n1sdp/disable-kvm.cfg
@@ -0,0 +1,5 @@
+define KMACHINE n1sdp
+define KTYPE standard
+define KARCH arm64
+
+include ktypes/standard/standard.scc
@@ -0,0 +1 @@
+# CONFIG_KVM is not set
@@ -0,0 +1,4 @@
+CONFIG_NET_9P=y
+CONFIG_NET_9P_VIRTIO=y
+CONFIG_9P_FS=y
+CONFIG_9P_FS_POSIX_ACL=y
@@ -0,0 +1 @@
+kconf non-hardware virtio-9p.cfg
@@ -0,0 +1,221 @@
+From 19eabe2a5fb97530820dd2a22fe6bc143a8d693f Mon Sep 17 00:00:00 2001
+From: Emekcan <emekcan.aras@arm.com>
+Date: Fri, 19 Aug 2022 14:51:08 +0100
+Subject: [PATCH 2/6] Add external system driver
+
+Adds external system driver to control it
+from user-space. It provides run and reset
+functionality at the moment.
+
+Upstream-Status: Pending [Not submitted to upstream yet]
+Signed-off-by: Emekcan Aras <emekcan.aras@arm.com>
+Signed-off-by: Rui Miguel Silva <rui.silva@linaro.org>
+---
+ drivers/misc/Kconfig           |   1 +
+ drivers/misc/Makefile          |   1 +
+ drivers/misc/arm/Kconfig       |   5 ++
+ drivers/misc/arm/Makefile      |   1 +
+ drivers/misc/arm/extsys_ctrl.c | 151 +++++++++++++++++++++++++++++++++
+ 5 files changed, 159 insertions(+)
+ create mode 100644 drivers/misc/arm/Kconfig
+ create mode 100644 drivers/misc/arm/Makefile
+ create mode 100644 drivers/misc/arm/extsys_ctrl.c
+
+diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig
+index 358ad56f6524..fd8654ffdab0 100644
+--- a/drivers/misc/Kconfig
+++ b/drivers/misc/Kconfig
+@@ -514,4 +514,5 @@ source "drivers/misc/habanalabs/Kconfig"
+ source "drivers/misc/uacce/Kconfig"
+ source "drivers/misc/pvpanic/Kconfig"
+ source "drivers/misc/mchp_pci1xxxx/Kconfig"
+source "drivers/misc/arm/Kconfig"
+ endmenu
+diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile
+index ac9b3e757ba1..f7852e4fd63d 100644
+--- a/drivers/misc/Makefile
+++ b/drivers/misc/Makefile
+@@ -62,3 +62,4 @@ obj-$(CONFIG_HI6421V600_IRQ)	+= hi6421v600-irq.o
+ obj-$(CONFIG_OPEN_DICE)		+= open-dice.o
+ obj-$(CONFIG_GP_PCI1XXXX)	+= mchp_pci1xxxx/
+ obj-$(CONFIG_VCPU_STALL_DETECTOR)	+= vcpu_stall_detector.o
+obj-y				+= arm/
+diff --git a/drivers/misc/arm/Kconfig b/drivers/misc/arm/Kconfig
+new file mode 100644
+index 000000000000..9f1eb284e530
+--- /dev/null
+++ b/drivers/misc/arm/Kconfig
+@@ -0,0 +1,5 @@
+config EXTSYS_CTRL
+	tristate "Arm External System control driver"
+	help
+	  Say y here to enable support for external system control
+	  driver for the Arm Corstone-700 and Corstone1000 platform
+\ No newline at end of file
+diff --git a/drivers/misc/arm/Makefile b/drivers/misc/arm/Makefile
+new file mode 100644
+index 000000000000..1ca3084cf8a0
+--- /dev/null
+++ b/drivers/misc/arm/Makefile
+@@ -0,0 +1 @@
+obj-$(CONFIG_EXTSYS_CTRL)	+= extsys_ctrl.o
+diff --git a/drivers/misc/arm/extsys_ctrl.c b/drivers/misc/arm/extsys_ctrl.c
+new file mode 100644
+index 000000000000..7929070ff43d
+--- /dev/null
+++ b/drivers/misc/arm/extsys_ctrl.c
+@@ -0,0 +1,151 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Arm Corstone700 and Corstone1000 external system reset control driver
+ *
+ * Copyright (C) 2019 Arm Ltd.
+ *
+ */
+
+#include <linux/fs.h>
+#include <linux/clk.h>
+#include <linux/err.h>
+#include <linux/interrupt.h>
+#include <linux/io.h>
+#include <linux/kernel.h>
+#include <linux/mod_devicetable.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/miscdevice.h>
+#include <linux/init.h>
+
+#define EXTSYS_DRV_NAME		"extsys_ctrl"
+#define EXTSYS_MAX_DEVS		 4
+
+#define EXTSYS_RST_SIZE		U(0x8)
+#define EXTSYS_RST_CTRL_OFF	U(0x0)
+#define EXTSYS_RST_ST_OFF	U(0x4)
+
+/* External system reset control indexes */
+#define EXTSYS_CPU_WAIT		(0x0)
+#define EXTSYS_RST_REQ		(0x1)
+
+/* External system reset status masks */
+#define EXTSYS_RST_ST_ACK_OFF	U(0x1)
+
+/* No Reset Requested */
+#define EXTSYS_RST_ST_ACK_NRR	(0x0 << EXTSYS_RST_ST_ACK_OFF)
+
+/* Reset Request Complete */
+#define EXTSYS_RST_ST_ACK_RRC	(0x2 << EXTSYS_RST_ST_ACK_OFF)
+
+/* Reset Request Unable to Complete */
+#define EXTSYS_RST_ST_ACK_RRUC	(0x3 << EXTSYS_RST_ST_ACK_OFF)
+
+/* IOCTL commands */
+#define EXTSYS_CPU_WAIT_DISABLE	0x0
+#define EXTSYS_RESET_REQ_ENABLE	0x1
+
+struct extsys_ctrl {
+	struct miscdevice miscdev;
+	void __iomem *reset_reg;
+	void __iomem *set_reg;
+};
+
+#define CLEAR_BIT(addr, index) writel(readl(addr) & ~(1UL << index), addr)
+#define SET_BIT(addr, index) writel(readl(addr) | (1UL << index), addr)
+
+static long extsys_ctrl_ioctl(struct file *f, unsigned int cmd,
+			      unsigned long arg)
+{
+	struct extsys_ctrl *extsys;
+
+	extsys = container_of(f->private_data, struct extsys_ctrl, miscdev);
+
+	switch (cmd) {
+	case EXTSYS_CPU_WAIT_DISABLE:
+		CLEAR_BIT(extsys->reset_reg, EXTSYS_CPU_WAIT);
+		break;
+	case EXTSYS_RESET_REQ_ENABLE:
+		SET_BIT(extsys->reset_reg, EXTSYS_RST_REQ);
+		break;
+	default:
+		break;
+	}
+
+	return 0;
+}
+
+static const struct file_operations extsys_ctrl_fops = {
+	.owner = THIS_MODULE,
+	.unlocked_ioctl = extsys_ctrl_ioctl,
+};
+
+static int extsys_ctrl_probe(struct platform_device *pdev)
+{
+	struct device *dev = &pdev->dev;
+	struct extsys_ctrl *extsys;
+	struct resource *res;
+	void __iomem *reset_reg;
+	void __iomem *set_reg;
+	int ret;
+
+	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "rstreg");
+	reset_reg = devm_ioremap_resource(dev, res);
+	if (IS_ERR(reset_reg))
+		return PTR_ERR(reset_reg);
+
+	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "streg");
+	set_reg = devm_ioremap_resource(dev, res);
+	if (IS_ERR(set_reg))
+		return PTR_ERR(set_reg);
+
+	extsys = devm_kzalloc(dev, sizeof(*extsys), GFP_KERNEL);
+	if (!extsys)
+		return -ENOMEM;
+
+	extsys->reset_reg = reset_reg;
+	extsys->set_reg = set_reg;
+
+	extsys->miscdev.minor = MISC_DYNAMIC_MINOR;
+	extsys->miscdev.name = EXTSYS_DRV_NAME;
+	extsys->miscdev.fops = &extsys_ctrl_fops;
+	extsys->miscdev.parent = dev;
+
+	ret = misc_register(&extsys->miscdev);
+	if (ret)
+		return ret;
+
+	dev_info(dev, "external system controller ready\n");
+
+	return 0;
+}
+
+static int extsys_ctrl_remove(struct platform_device *pdev)
+{
+	struct extsys_ctrl *extsys = dev_get_drvdata(&pdev->dev);
+
+	misc_deregister(&extsys->miscdev);
+
+	return 0;
+}
+
+static const struct of_device_id extsys_ctrl_match[] = {
+	{ .compatible = "arm,extsys_ctrl" },
+	{ },
+};
+MODULE_DEVICE_TABLE(of, extsys_ctrl_match);
+
+static struct platform_driver extsys_ctrl_driver = {
+	.driver = {
+		.name = EXTSYS_DRV_NAME,
+		.of_match_table = extsys_ctrl_match,
+	},
+	.probe = extsys_ctrl_probe,
+	.remove = extsys_ctrl_remove,
+};
+module_platform_driver(extsys_ctrl_driver);
+
+MODULE_LICENSE("GPL v2");
+MODULE_DESCRIPTION("Arm External System Control Driver");
+MODULE_AUTHOR("Morten Borup Petersen");
+MODULE_AUTHOR("Rui Miguel Silva <rui.silva@arm.com>");
+-- 
+2.39.0
+
@@ -0,0 +1,221 @@
+From 9fb971c23d423f593620ed82fb69a7e2cd35986a Mon Sep 17 00:00:00 2001
+From: Emekcan <emekcan.aras@arm.com>
+Date: Wed, 17 Aug 2022 14:21:42 +0100
+Subject: [PATCH 3/6] Add rpmsg driver for corstone1000
+
+Adds rpmsg driver to communicate with external
+system in corstone1000 platform.
+
+Upstream-Status: Pending
+Signed-off-by: Emekcan Aras <emekcan.aras@arm.com>
+Signed-off-by: Rui Miguel Silva <rui.silva@linaro.org>
+---
+ drivers/rpmsg/Kconfig             |  10 ++
+ drivers/rpmsg/Makefile            |   1 +
+ drivers/rpmsg/rpmsg_arm_mailbox.c | 164 ++++++++++++++++++++++++++++++
+ 3 files changed, 175 insertions(+)
+ create mode 100644 drivers/rpmsg/rpmsg_arm_mailbox.c
+
+diff --git a/drivers/rpmsg/Kconfig b/drivers/rpmsg/Kconfig
+index d3795860f5c0..fc6916d7b523 100644
+--- a/drivers/rpmsg/Kconfig
+++ b/drivers/rpmsg/Kconfig
+@@ -81,4 +81,14 @@ config RPMSG_VIRTIO
+ 	select RPMSG_NS
+ 	select VIRTIO
+ 
+config RPMSG_ARM
+	tristate "ARM RPMSG driver"
+	select     RPMSG
+	depends on HAS_IOMEM
+	depends on MAILBOX
+	help
+	  Say y here to enable support for rpmsg lient driver which is built
+	  around mailbox client using Arm MHUv2.1 as physical medium.This
+	  driver enables communication which remote processor using MHU.
+
+ endmenu
+diff --git a/drivers/rpmsg/Makefile b/drivers/rpmsg/Makefile
+index 58e3b382e316..6bdcc69688b2 100644
+--- a/drivers/rpmsg/Makefile
+++ b/drivers/rpmsg/Makefile
+@@ -1,5 +1,6 @@
+ # SPDX-License-Identifier: GPL-2.0
+ obj-$(CONFIG_RPMSG)		+= rpmsg_core.o
+obj-$(CONFIG_RPMSG_ARM)		+= rpmsg_arm_mailbox.o
+ obj-$(CONFIG_RPMSG_CHAR)	+= rpmsg_char.o
+ obj-$(CONFIG_RPMSG_CTRL)	+= rpmsg_ctrl.o
+ obj-$(CONFIG_RPMSG_NS)		+= rpmsg_ns.o
+diff --git a/drivers/rpmsg/rpmsg_arm_mailbox.c b/drivers/rpmsg/rpmsg_arm_mailbox.c
+new file mode 100644
+index 000000000000..4a80102669f6
+--- /dev/null
+++ b/drivers/rpmsg/rpmsg_arm_mailbox.c
+@@ -0,0 +1,164 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * rpmsg client driver using mailbox client interface
+ *
+ * Copyright (C) 2019 ARM Ltd.
+ *
+ */
+
+#include <linux/bitmap.h>
+#include <linux/export.h>
+#include <linux/io.h>
+#include <linux/kernel.h>
+#include <linux/ktime.h>
+#include <linux/mailbox_client.h>
+#include <linux/module.h>
+#include <linux/of_address.h>
+#include <linux/of_device.h>
+#include <linux/processor.h>
+#include <linux/semaphore.h>
+#include <linux/slab.h>
+#include <linux/rpmsg.h>
+#include "rpmsg_internal.h"
+#include <linux/mailbox/arm_mhuv2_message.h>
+
+#define RPMSG_NAME	"arm_rpmsg"
+#define RPMSG_ADDR_ANY	0xFFFFFFFF
+
+struct arm_channel {
+	struct rpmsg_endpoint ept;
+	struct mbox_client cl;
+	struct mbox_chan *mbox;
+};
+
+#define arm_channel_from_rpmsg(_ept) container_of(_ept, struct arm_channel, ept)
+#define arm_channel_from_mbox(_ept) container_of(_ept, struct arm_channel, cl)
+
+
+static void arm_msg_rx_handler(struct mbox_client *cl, void *mssg)
+{
+	struct arm_mhuv2_mbox_msg *msg = mssg;
+	struct arm_channel* channel = arm_channel_from_mbox(cl);
+	int err = channel->ept.cb(channel->ept.rpdev, msg->data, 4, channel->ept.priv, RPMSG_ADDR_ANY);
+	if(err) {
+		printk("ARM Mailbox: Endpoint callback failed with error: %d", err);
+	}
+}
+
+
+static void arm_destroy_ept(struct rpmsg_endpoint *ept)
+{
+	struct arm_channel *channel = arm_channel_from_rpmsg(ept);
+	mbox_free_channel(channel->mbox);
+	kfree(channel);
+}
+
+static int arm_send(struct rpmsg_endpoint *ept, void *data, int len)
+{
+	struct arm_channel *channel = arm_channel_from_rpmsg(ept);
+
+	mbox_send_message(channel->mbox, data);
+	return 0;
+}
+
+static int arm_sendto(struct rpmsg_endpoint *ept, void *data, int len, u32 dest)
+{
+	struct arm_mhuv2_mbox_msg msg;
+	struct arm_channel *channel = arm_channel_from_rpmsg(ept);
+	msg.data = data;
+	msg.len = len;
+	mbox_send_message(channel->mbox, &msg);
+	return 0;
+}
+
+
+static const struct rpmsg_endpoint_ops arm_endpoint_ops = {
+	.destroy_ept = arm_destroy_ept,
+	.send = arm_send,
+	.sendto = arm_sendto,
+};
+
+
+static struct rpmsg_endpoint *arm_create_ept(struct rpmsg_device *rpdev,
+		rpmsg_rx_cb_t cb, void *priv, struct rpmsg_channel_info chinfo)
+{
+	struct arm_channel *channel;
+
+	channel = kzalloc(sizeof(*channel), GFP_KERNEL);
+
+	// Initialize rpmsg endpoint
+	kref_init(&channel->ept.refcount);
+	channel->ept.rpdev = rpdev;
+	channel->ept.cb = cb;
+	channel->ept.priv = priv;
+	channel->ept.ops = &arm_endpoint_ops;
+
+	// Initialize mailbox client
+	channel->cl.dev = rpdev->dev.parent;
+	channel->cl.rx_callback = arm_msg_rx_handler;
+	channel->cl.tx_done = NULL; /* operate in blocking mode */
+	channel->cl.tx_block = true;
+	channel->cl.tx_tout = 500; /* by half a second */
+	channel->cl.knows_txdone = false; /* depending upon protocol */
+
+	channel->mbox = mbox_request_channel_byname(&channel->cl, chinfo.name);
+	if (IS_ERR_OR_NULL(channel->mbox)) {
+		printk("RPMsg ARM: Cannot get channel by name: '%s'\n", chinfo.name);
+		return -1;
+	}
+
+	return &channel->ept;
+}
+
+static const struct rpmsg_device_ops arm_device_ops = {
+	.create_ept = arm_create_ept,
+};
+
+
+static void arm_release_device(struct device *dev)
+{
+	struct rpmsg_device *rpdev = to_rpmsg_device(dev);
+
+	kfree(rpdev);
+}
+
+
+static int client_probe(struct platform_device *pdev)
+{
+	struct device *dev = &pdev->dev;
+	struct rpmsg_device *rpdev;
+
+	rpdev = kzalloc(sizeof(*rpdev), GFP_KERNEL);
+	if (!rpdev)
+		return -ENOMEM;
+
+	/* Assign callbacks for rpmsg_device */
+	rpdev->ops = &arm_device_ops;
+
+	/* Assign public information to the rpmsg_device */
+	memcpy(rpdev->id.name, RPMSG_NAME, strlen(RPMSG_NAME));
+
+	rpdev->dev.parent = dev;
+	rpdev->dev.release = arm_release_device;
+
+	return rpmsg_chrdev_register_device(rpdev);
+}
+
+static const struct of_device_id client_of_match[] = {
+	{ .compatible = "arm,client", .data = NULL },
+	{ /* Sentinel */ },
+};
+
+static struct platform_driver client_driver = {
+	.driver = {
+		.name = "arm-mhu-client",
+		.of_match_table = client_of_match,
+	},
+	.probe = client_probe,
+};
+
+module_platform_driver(client_driver);
+
+MODULE_LICENSE("GPL v2");
+MODULE_DESCRIPTION("ARM RPMSG Driver");
+MODULE_AUTHOR("Tushar Khandelwal <tushar.khandelwal@arm.com>");
+-- 
+2.39.0
+
@@ -0,0 +1,33 @@
+From ce77351c8ae6b04070135fdaedaad337bb0b4ef5 Mon Sep 17 00:00:00 2001
+From: Rui Miguel Silva <rui.silva@linaro.org>
+Date: Tue, 27 Sep 2022 10:05:27 +0100
+Subject: [PATCH 4/6] rpmsg: arm: fix return value
+
+The creation of and endpoint returns a pointer, fix the return
+value to the right type.
+
+Upstream-Status: Pending
+Signed-off-by: Rui Miguel Silva <rui.silva@linaro.org>
+---
+ drivers/rpmsg/rpmsg_arm_mailbox.c | 5 +++--
+ 1 file changed, 3 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/rpmsg/rpmsg_arm_mailbox.c b/drivers/rpmsg/rpmsg_arm_mailbox.c
+index 4a80102669f6..5c0dcc8e353d 100644
+--- a/drivers/rpmsg/rpmsg_arm_mailbox.c
+++ b/drivers/rpmsg/rpmsg_arm_mailbox.c
+@@ -103,8 +103,9 @@ static struct rpmsg_endpoint *arm_create_ept(struct rpmsg_device *rpdev,
+ 
+ 	channel->mbox = mbox_request_channel_byname(&channel->cl, chinfo.name);
+ 	if (IS_ERR_OR_NULL(channel->mbox)) {
+-		printk("RPMsg ARM: Cannot get channel by name: '%s'\n", chinfo.name);
+-		return -1;
+		printk("RPMsg ARM: Cannot get channel by name: %s\n",
+		       chinfo.name);
+		return ERR_PTR(-ENOENT);
+ 	}
+ 
+ 	return &channel->ept;
+-- 
+2.39.0
+
@@ -0,0 +1,31 @@
+From 590bf152e18b3cf7166c7accfc32ed3b2d07bf09 Mon Sep 17 00:00:00 2001
+From: Rui Miguel Silva <rui.silva@linaro.org>
+Date: Tue, 27 Sep 2022 10:07:21 +0100
+Subject: [PATCH 5/6] rpmsg: arm: update chrdev to ctrldev registration
+
+Since "rpmsg: Update rpmsg_chrdev_register_device function",
+there was a replacement of the chrdev driver to ctrldev
+driver. Fix the registration.
+
+Upstream-Status: Pending
+Signed-off-by: Rui Miguel Silva <rui.silva@linaro.org>
+---
+ drivers/rpmsg/rpmsg_arm_mailbox.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/rpmsg/rpmsg_arm_mailbox.c b/drivers/rpmsg/rpmsg_arm_mailbox.c
+index 5c0dcc8e353d..90bc8df90885 100644
+--- a/drivers/rpmsg/rpmsg_arm_mailbox.c
+++ b/drivers/rpmsg/rpmsg_arm_mailbox.c
+@@ -142,7 +142,7 @@ static int client_probe(struct platform_device *pdev)
+ 	rpdev->dev.parent = dev;
+ 	rpdev->dev.release = arm_release_device;
+ 
+-	return rpmsg_chrdev_register_device(rpdev);
+	return rpmsg_ctrldev_register_device(rpdev);
+ }
+ 
+ static const struct of_device_id client_of_match[] = {
+-- 
+2.39.0
+
@@ -0,0 +1,40 @@
+From 00851c43f4d00e7451550660ab652e9ac9128e02 Mon Sep 17 00:00:00 2001
+From: Emekcan <emekcan.aras@arm.com>
+Date: Thu, 13 Oct 2022 20:53:42 +0100
+Subject: [PATCH 6/6] Adds workaround for cs1k specific bug
+
+Adds a temporary workaround to solve a possible
+race-conditioning issue in the tee driver
+for corstone1000.
+
+Upstream-Status: Inappropriate
+Signed-off-by: Emekcan Aras <emekcan.aras@arm.com>
+Signed-off-by: Rui Miguel Silva <rui.silva@linaro.org>
+---
+ drivers/firmware/arm_ffa/driver.c | 3 ++-
+ 1 file changed, 2 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/firmware/arm_ffa/driver.c b/drivers/firmware/arm_ffa/driver.c
+index d5e86ef40b89..cbb944f63321 100644
+--- a/drivers/firmware/arm_ffa/driver.c
+++ b/drivers/firmware/arm_ffa/driver.c
+@@ -32,6 +32,7 @@
+ #include <linux/scatterlist.h>
+ #include <linux/slab.h>
+ #include <linux/uuid.h>
+#include <linux/delay.h>
+ 
+ #include "common.h"
+ 
+@@ -362,7 +363,7 @@ static int ffa_msg_send_direct_req(u16 src_id, u16 dst_id, bool mode_32bit,
+ {
+ 	u32 req_id, resp_id, src_dst_ids = PACK_TARGET_INFO(src_id, dst_id);
+ 	ffa_value_t ret;
+-
+	msleep(1);
+ 	if (mode_32bit) {
+ 		req_id = FFA_MSG_SEND_DIRECT_REQ;
+ 		resp_id = FFA_MSG_SEND_DIRECT_RESP;
+-- 
+2.39.0
+
@@ -0,0 +1,3 @@
+CONFIG_DEBUG_INFO=y
+CONFIG_DEBUG_KERNEL=y
+CONFIG_DEBUG_INFO_DWARF4=y
@@ -0,0 +1,100 @@
+CONFIG_LOCALVERSION="-yocto-standard"
+# CONFIG_LOCALVERSION_AUTO is not set
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_PREEMPT=y
+CONFIG_LOG_BUF_SHIFT=13
+CONFIG_LOG_CPU_MAX_BUF_SHIFT=13
+CONFIG_RELAY=y
+CONFIG_BOOT_CONFIG=y
+CONFIG_ARCH_VEXPRESS=y
+CONFIG_CMDLINE="console=ttyAMA0 loglevel=9"
+CONFIG_EFI=y
+# CONFIG_SUSPEND is not set
+CONFIG_EFI_BOOTLOADER_CONTROL=y
+CONFIG_EFI_CAPSULE_LOADER=y
+CONFIG_EFI_TEST=y
+CONFIG_RESET_ATTACK_MITIGATION=y
+# CONFIG_STACKPROTECTOR is not set
+CONFIG_MODULES=y
+# CONFIG_BLK_DEV_BSG is not set
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+CONFIG_NET=y
+CONFIG_PACKET=y
+CONFIG_UNIX=y
+CONFIG_INET=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_IP_PNP_BOOTP=y
+CONFIG_SYN_COOKIES=y
+CONFIG_NET_SCHED=y
+CONFIG_DEVTMPFS=y
+CONFIG_SCSI=y
+CONFIG_BLK_DEV_SD=y
+CONFIG_NETDEVICES=y
+# CONFIG_NET_VENDOR_ALACRITECH is not set
+# CONFIG_NET_VENDOR_AMAZON is not set
+# CONFIG_NET_VENDOR_AMD is not set
+# CONFIG_NET_VENDOR_AQUANTIA is not set
+# CONFIG_NET_VENDOR_ARC is not set
+# CONFIG_NET_VENDOR_BROADCOM is not set
+# CONFIG_NET_VENDOR_CADENCE is not set
+# CONFIG_NET_VENDOR_CAVIUM is not set
+# CONFIG_NET_VENDOR_CORTINA is not set
+# CONFIG_NET_VENDOR_EZCHIP is not set
+# CONFIG_NET_VENDOR_GOOGLE is not set
+# CONFIG_NET_VENDOR_HISILICON is not set
+# CONFIG_NET_VENDOR_HUAWEI is not set
+# CONFIG_NET_VENDOR_INTEL is not set
+# CONFIG_NET_VENDOR_MARVELL is not set
+# CONFIG_NET_VENDOR_MICREL is not set
+# CONFIG_NET_VENDOR_MICROCHIP is not set
+# CONFIG_NET_VENDOR_MICROSEMI is not set
+# CONFIG_NET_VENDOR_NATSEMI is not set
+# CONFIG_NET_VENDOR_NETRONOME is not set
+# CONFIG_NET_VENDOR_NI is not set
+# CONFIG_NET_VENDOR_PENSANDO is not set
+# CONFIG_NET_VENDOR_QUALCOMM is not set
+# CONFIG_NET_VENDOR_RENESAS is not set
+# CONFIG_NET_VENDOR_ROCKER is not set
+# CONFIG_NET_VENDOR_SAMSUNG is not set
+# CONFIG_NET_VENDOR_SEEQ is not set
+# CONFIG_NET_VENDOR_SOLARFLARE is not set
+CONFIG_SMC91X=y
+CONFIG_SMSC911X=y
+# CONFIG_NET_VENDOR_SOCIONEXT is not set
+# CONFIG_NET_VENDOR_STMICRO is not set
+# CONFIG_NET_VENDOR_SYNOPSYS is not set
+# CONFIG_NET_VENDOR_VIA is not set
+# CONFIG_NET_VENDOR_WIZNET is not set
+# CONFIG_NET_VENDOR_XILINX is not set
+# CONFIG_SERIO_SERPORT is not set
+CONFIG_SERIAL_AMBA_PL011=y
+CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
+CONFIG_USB=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_UAS=y
+CONFIG_USB_ISP1760=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_DRV_PL031=y
+CONFIG_TEE=y
+CONFIG_OPTEE=y
+CONFIG_VFAT_FS=y
+CONFIG_TMPFS=y
+CONFIG_CONFIGFS_FS=y
+CONFIG_NLS_CODEPAGE_437=y
+CONFIG_NLS_CODEPAGE_860=y
+CONFIG_NLS_ISO8859_1=y
+CONFIG_NLS_ISO8859_15=y
+CONFIG_NLS_UTF8=y
+CONFIG_LIBCRC32C=y
+# CONFIG_SECTION_MISMATCH_WARN_ONLY is not set
+CONFIG_DEBUG_FS=y
+CONFIG_PANIC_TIMEOUT=5
+CONFIG_STACKTRACE=y
+CONFIG_EXTSYS_CTRL=y
+CONFIG_MAILBOX=y
+CONFIG_ARM_MHU_V2=y
+CONFIG_RPMSG=y
+CONFIG_RPMSG_CHAR=y
+CONFIG_RPMSG_ARM=y
+CONFIG_RPMSG_CTRL=y
@@ -0,0 +1,29 @@
+From b443c8efd563dc372c60e7ad9f52aeddf7c13706 Mon Sep 17 00:00:00 2001
+From: Anton Antonov <Anton.Antonov@arm.com>
+Date: Mon, 7 Nov 2022 11:37:51 +0000
+Subject: [PATCH] arm64: dts: fvp: Enable virtio-rng support
+
+The virtio-rng is available from FVP_Base_RevC-2xAEMvA version 11.17.
+Enable it since Yocto includes a recipe for a newer FVP version.
+
+Upstream-Status: Inappropriate [Yocto specific]
+Signed-off-by: Anton Antonov <Anton.Antonov@arm.com>
+---
+ arch/arm64/boot/dts/arm/rtsm_ve-motherboard-rs2.dtsi | 1 -
+ 1 file changed, 1 deletion(-)
+
+diff --git a/arch/arm64/boot/dts/arm/rtsm_ve-motherboard-rs2.dtsi b/arch/arm64/boot/dts/arm/rtsm_ve-motherboard-rs2.dtsi
+index ec2d5280a30b..acafdcbf1063 100644
+--- a/arch/arm64/boot/dts/arm/rtsm_ve-motherboard-rs2.dtsi
+++ b/arch/arm64/boot/dts/arm/rtsm_ve-motherboard-rs2.dtsi
+@@ -26,7 +26,6 @@ virtio@200000 {
+ 					compatible = "virtio,mmio";
+ 					reg = <0x200000 0x200>;
+ 					interrupts = <46>;
+-					status = "disabled";
+ 				};
+ 			};
+ 		};
+-- 
+2.25.1
+
@@ -0,0 +1,212 @@
+/dts-v1/;
+
+/ {
+
+        #address-cells = <0x2>;
+        #size-cells = <0x2>;
+        interrupt-parent = <0x1>;
+        model = "Generated";
+        compatible = "arm,base";
+
+        memory@0 {
+                #address-cells = <0x2>;
+                #size-cells = <0x2>;
+                device_type = "memory";
+                reg = <0x0        0x0        0x0 0x80000000>,
+                      <0x00000008 0x80000000 0x0 0x80000000>;
+        };
+
+        cpus {
+                #address-cells = <0x2>;
+                #size-cells = <0x0>;
+
+                cpu-map {
+                        cluster0 {
+                                core0 { thread0 { cpu = <&CPU_0>; }; };
+                                core1 { thread0 { cpu = <&CPU_1>; }; };
+                                core2 { thread0 { cpu = <&CPU_2>; }; };
+                                core3 { thread0 { cpu = <&CPU_3>; }; };
+                        };
+                };
+
+                CPU_0: cpu@0 {
+                        device_type = "cpu";
+                        compatible = "arm,armv8";
+                        reg = <0x0 0x0>;
+                        enable-method = "spin-table";
+                        cpu-release-addr = <0x0 0x7f800>;
+                };
+
+                CPU_1: cpu@1 {
+                        device_type = "cpu";
+                        compatible = "arm,armv8";
+                        reg = <0x0 0x1>;
+                        enable-method = "spin-table";
+                        cpu-release-addr = <0x0 0x7f808>;
+                };
+
+                CPU_2: cpu@2 {
+                        device_type = "cpu";
+                        compatible = "arm,armv8";
+                        reg = <0x0 0x2>;
+                        enable-method = "spin-table";
+                        cpu-release-addr = <0x0 0x7f810>;
+                };
+
+                CPU_3: cpu@3 {
+                        device_type = "cpu";
+                        compatible = "arm,armv8";
+                        reg = <0x0 0x3>;
+                        enable-method = "spin-table";
+                        cpu-release-addr = <0x0 0x7f818>;
+                };
+        };
+
+        interrupt-controller@af000000 {
+                compatible = "arm,gic-v3";
+                #interrupt-cells = <0x3>;
+                #address-cells = <0x2>;
+                #size-cells = <0x2>;
+                ranges;
+                interrupt-controller;
+                #redistributor-regions = <0x1>;
+                reg = <0x0 0xaf000000 0x0 0x10000>,     // GICD
+                      <0x0 0xaf100000 0x0 0x100000>,    // GICR
+                      <0x0 0xac000000 0x0 0x2000>,      // GICC
+                      <0x0 0xac010000 0x0 0x2000>,      // GICH
+                      <0x0 0xac02f000 0x0 0x2000>;      // GICV
+                interrupts = <0x1 9 0x4>;
+                linux,phandle = <0x1>;
+                phandle = <0x1>;
+
+                its: msi-controller@2f020000 {
+                        #msi-cells = <1>;
+                        compatible = "arm,gic-v3-its";
+                        reg = <0x0 0xaf020000 0x0 0x20000>; // GITS
+                        msi-controller;
+                };
+
+        };
+
+        refclk100mhz: refclk100mhz {
+                compatible = "fixed-clock";
+                #clock-cells = <0>;
+                clock-frequency = <100000000>;
+                clock-output-names = "apb_pclk";
+        };
+
+        refclk24mhz: refclk24mhz {
+                compatible = "fixed-clock";
+                #clock-cells = <0>;
+                clock-frequency = <24000000>;
+                clock-output-names = "refclk24mhz";
+        };
+
+        refclk1hz: refclk1hz {
+                compatible = "fixed-clock";
+                #clock-cells = <0>;
+                clock-frequency = <1>;
+                clock-output-names = "refclk1hz";
+        };
+
+        uart@9c090000 {
+                compatible = "arm,pl011", "arm,primecell";
+                reg = <0x0 0x9c090000 0x0 0x1000>;
+                interrupts = <0x0 5 0x4>;
+                clocks = <&refclk24mhz>, <&refclk100mhz>;
+                clock-names = "uartclk", "apb_pclk";
+        };
+
+        uart@9c0a0000 {
+                compatible = "arm,pl011", "arm,primecell";
+                reg = <0x0 0x9c0a0000 0x0 0x1000>;
+                interrupts = <0x0 6 0x4>;
+                clocks = <&refclk24mhz>, <&refclk100mhz>;
+                clock-names = "uartclk", "apb_pclk";
+        };
+
+        uart@9c0b0000 {
+                compatible = "arm,pl011", "arm,primecell";
+                reg = <0x0 0x9c0b0000 0x0 0x1000>;
+                interrupts = <0x0 7 0x4>;
+                clocks = <&refclk24mhz>, <&refclk100mhz>;
+                clock-names = "uartclk", "apb_pclk";
+        };
+
+        uart@9c0c0000 {
+                compatible = "arm,pl011", "arm,primecell";
+                reg = <0x0 0x9c0c0000 0x0 0x1000>;
+                interrupts = <0x0 8 0x4>;
+                clocks = <&refclk24mhz>, <&refclk100mhz>;
+                clock-names = "uartclk", "apb_pclk";
+        };
+
+        wdt@9c0f0000 {
+                compatible = "arm,sp805", "arm,primecell";
+                reg = <0x0 0x9c0f0000 0x0 0x1000>;
+                interrupts = <0x0 0 0x4>;
+                clocks = <&refclk24mhz>, <&refclk100mhz>;
+                clock-names = "wdog_clk", "apb_pclk";
+        };
+
+        rtc@9c170000 {
+                compatible = "arm,pl031", "arm,primecell";
+                reg = <0x0 0x9c170000 0x0 0x1000>;
+                interrupts = <0x0 4 0x4>;
+                clocks = <&refclk1hz>;
+                clock-names = "apb_pclk";
+        };
+
+        virtio-block@9c130000 {
+                compatible = "virtio,mmio";
+                reg = <0 0x9c130000 0 0x200>;
+                interrupts = <0x0 42 0x4>;
+        };
+
+        virtio-p9@9c140000{
+                compatible = "virtio,mmio";
+                reg = <0x0 0x9c140000 0x0 0x1000>;
+                interrupts = <0x0 43 0x4>;
+        };
+
+        virtio-net@9c150000 {
+                compatible = "virtio,mmio";
+                reg = <0 0x9c150000 0 0x200>;
+                interrupts = <0x0 44 0x4>;
+        };
+
+        virtio-rng@9c200000 {
+                compatible = "virtio,mmio";
+                reg = <0 0x9c200000 0 0x200>;
+                interrupts = <0x0 46 0x4>;
+        };
+
+        timer {
+                compatible = "arm,armv8-timer";
+                interrupts = <0x1 13 0xff08>,
+                             <0x1 14 0xff08>,
+                             <0x1 11 0xff08>,
+                             <0x1  4 0xff08>;
+                clock-frequency = <100000000>;
+        };
+
+        aliases {
+                serial0 = "/uart@9c090000";
+                serial1 = "/uart@9c0a0000";
+                serial2 = "/uart@9c0b0000";
+                serial3 = "/uart@9c0c0000";
+        };
+
+        pmu {
+                compatible = "arm,armv8-pmuv3";
+                interrupts = <0 60 4>,
+                             <0 61 4>,
+                             <0 62 4>,
+                             <0 63 4>;
+        };
+
+        chosen {
+                bootargs = "earlycon console=ttyAMA0 loglevel=8 rootfstype=ext4 root=/dev/vda1 rw";
+                stdout-path = "serial0";
+        };
+};
@@ -0,0 +1,138 @@
+From dc250cab31c6611cc7fa76bc8b2027dbd56dd65d Mon Sep 17 00:00:00 2001
+From: Pierre Gondois <pierre.gondois@arm.com>
+Date: Mon, 7 Nov 2022 16:56:58 +0100
+Subject: [PATCH] arm64: dts: Update cache properties for Arm Ltd platforms
+
+The DeviceTree Specification v0.3 specifies that the cache node
+"compatible" and "cache-level" properties are required.
+
+Cf. s3.8 Multi-level and Shared Cache Nodes
+The 'cache-unified' property should be present if one of the properties
+for unified cache is present ('cache-size', ...).
+
+Update the relevant device trees nodes accordingly.
+
+Signed-off-by: Pierre Gondois <pierre.gondois@arm.com>
+Link: https://lore.kernel.org/r/20221107155825.1644604-6-pierre.gondois@arm.com
+Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
+
+Signed-off-by: Jon Mason <jon.mason@arm.com>
+Upstream-Status: Backport
+---
+ arch/arm64/boot/dts/arm/corstone1000.dtsi            | 1 +
+ arch/arm64/boot/dts/arm/foundation-v8.dtsi           | 1 +
+ arch/arm64/boot/dts/arm/juno-r1.dts                  | 2 ++
+ arch/arm64/boot/dts/arm/juno-r2.dts                  | 2 ++
+ arch/arm64/boot/dts/arm/juno.dts                     | 2 ++
+ arch/arm64/boot/dts/arm/rtsm_ve-aemv8a.dts           | 1 +
+ arch/arm64/boot/dts/arm/vexpress-v2f-1xv7-ca53x2.dts | 1 +
+ 7 files changed, 10 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/arm/corstone1000.dtsi b/arch/arm64/boot/dts/arm/corstone1000.dtsi
+index 4e46826f883a..21f1f952e985 100644
+--- a/arch/arm64/boot/dts/arm/corstone1000.dtsi
+++ b/arch/arm64/boot/dts/arm/corstone1000.dtsi
+@@ -53,6 +53,7 @@ gic: interrupt-controller@1c000000 {
+ 
+ 	L2_0: l2-cache0 {
+ 		compatible = "cache";
+		cache-unified;
+ 		cache-level = <2>;
+ 		cache-size = <0x80000>;
+ 		cache-line-size = <64>;
+diff --git a/arch/arm64/boot/dts/arm/foundation-v8.dtsi b/arch/arm64/boot/dts/arm/foundation-v8.dtsi
+index 83e3e7e3984f..c8bd23b1a7ba 100644
+--- a/arch/arm64/boot/dts/arm/foundation-v8.dtsi
+++ b/arch/arm64/boot/dts/arm/foundation-v8.dtsi
+@@ -58,6 +58,7 @@ cpu3: cpu@3 {
+ 
+ 		L2_0: l2-cache0 {
+ 			compatible = "cache";
+			cache-level = <2>;
+ 		};
+ 	};
+ 
+diff --git a/arch/arm64/boot/dts/arm/juno-r1.dts b/arch/arm64/boot/dts/arm/juno-r1.dts
+index 6451c62146fd..1d90eeebb37d 100644
+--- a/arch/arm64/boot/dts/arm/juno-r1.dts
+++ b/arch/arm64/boot/dts/arm/juno-r1.dts
+@@ -189,6 +189,7 @@ A53_3: cpu@103 {
+ 
+ 		A57_L2: l2-cache0 {
+ 			compatible = "cache";
+			cache-unified;
+ 			cache-size = <0x200000>;
+ 			cache-line-size = <64>;
+ 			cache-sets = <2048>;
+@@ -197,6 +198,7 @@ A57_L2: l2-cache0 {
+ 
+ 		A53_L2: l2-cache1 {
+ 			compatible = "cache";
+			cache-unified;
+ 			cache-size = <0x100000>;
+ 			cache-line-size = <64>;
+ 			cache-sets = <1024>;
+diff --git a/arch/arm64/boot/dts/arm/juno-r2.dts b/arch/arm64/boot/dts/arm/juno-r2.dts
+index 438cd1ff4bd0..d2ada69b0a43 100644
+--- a/arch/arm64/boot/dts/arm/juno-r2.dts
+++ b/arch/arm64/boot/dts/arm/juno-r2.dts
+@@ -195,6 +195,7 @@ A53_3: cpu@103 {
+ 
+ 		A72_L2: l2-cache0 {
+ 			compatible = "cache";
+			cache-unified;
+ 			cache-size = <0x200000>;
+ 			cache-line-size = <64>;
+ 			cache-sets = <2048>;
+@@ -203,6 +204,7 @@ A72_L2: l2-cache0 {
+ 
+ 		A53_L2: l2-cache1 {
+ 			compatible = "cache";
+			cache-unified;
+ 			cache-size = <0x100000>;
+ 			cache-line-size = <64>;
+ 			cache-sets = <1024>;
+diff --git a/arch/arm64/boot/dts/arm/juno.dts b/arch/arm64/boot/dts/arm/juno.dts
+index cf4a58211399..5e48a01a5b9f 100644
+--- a/arch/arm64/boot/dts/arm/juno.dts
+++ b/arch/arm64/boot/dts/arm/juno.dts
+@@ -194,6 +194,7 @@ A53_3: cpu@103 {
+ 
+ 		A57_L2: l2-cache0 {
+ 			compatible = "cache";
+			cache-unified;
+ 			cache-size = <0x200000>;
+ 			cache-line-size = <64>;
+ 			cache-sets = <2048>;
+@@ -202,6 +203,7 @@ A57_L2: l2-cache0 {
+ 
+ 		A53_L2: l2-cache1 {
+ 			compatible = "cache";
+			cache-unified;
+ 			cache-size = <0x100000>;
+ 			cache-line-size = <64>;
+ 			cache-sets = <1024>;
+diff --git a/arch/arm64/boot/dts/arm/rtsm_ve-aemv8a.dts b/arch/arm64/boot/dts/arm/rtsm_ve-aemv8a.dts
+index 258991ad7cc0..ef68f5aae7dd 100644
+--- a/arch/arm64/boot/dts/arm/rtsm_ve-aemv8a.dts
+++ b/arch/arm64/boot/dts/arm/rtsm_ve-aemv8a.dts
+@@ -71,6 +71,7 @@ cpu@3 {
+ 
+ 		L2_0: l2-cache0 {
+ 			compatible = "cache";
+			cache-level = <2>;
+ 		};
+ 	};
+ 
+diff --git a/arch/arm64/boot/dts/arm/vexpress-v2f-1xv7-ca53x2.dts b/arch/arm64/boot/dts/arm/vexpress-v2f-1xv7-ca53x2.dts
+index 5b6d9d8e934d..796cd7d02eb5 100644
+--- a/arch/arm64/boot/dts/arm/vexpress-v2f-1xv7-ca53x2.dts
+++ b/arch/arm64/boot/dts/arm/vexpress-v2f-1xv7-ca53x2.dts
+@@ -57,6 +57,7 @@ cpu@1 {
+ 
+ 		L2_0: l2-cache0 {
+ 			compatible = "cache";
+			cache-level = <2>;
+ 		};
+ 	};
+ 
@@ -0,0 +1,35 @@
+From bd354219987dddbf8ab6fd11450b4046547aca1b Mon Sep 17 00:00:00 2001
+From: James Clark <james.clark@arm.com>
+Date: Thu, 17 Nov 2022 10:25:36 +0000
+Subject: [PATCH] arm64: dts: fvp: Add SPE to Foundation FVP
+
+Add SPE DT node to FVP model. If the model doesn't support SPE (e.g.,
+turned off via parameter), the driver will skip the initialisation
+accordingly and thus is safe.
+
+Signed-off-by: James Clark <james.clark@arm.com>
+Link: https://lore.kernel.org/r/20221117102536.237515-1-james.clark@arm.com
+Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
+
+Signed-off-by: Jon Mason <jon.mason@arm.com>
+Upstream-Status: Backport
+---
+ arch/arm64/boot/dts/arm/foundation-v8.dtsi | 5 +++++
+ 1 file changed, 5 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/arm/foundation-v8.dtsi b/arch/arm64/boot/dts/arm/foundation-v8.dtsi
+index c8bd23b1a7ba..029578072d8f 100644
+--- a/arch/arm64/boot/dts/arm/foundation-v8.dtsi
+++ b/arch/arm64/boot/dts/arm/foundation-v8.dtsi
+@@ -85,6 +85,11 @@ pmu {
+ 			     <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
+ 	};
+ 
+	spe-pmu {
+		compatible = "arm,statistical-profiling-extension-v1";
+		interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>;
+	};
+
+ 	watchdog@2a440000 {
+ 		compatible = "arm,sbsa-gwdt";
+ 		reg = <0x0 0x2a440000 0 0x1000>,
@@ -0,0 +1,146 @@
+From 22e740d069e14875a64864bf86e0826a96560b44 Mon Sep 17 00:00:00 2001
+From: Sudeep Holla <sudeep.holla@arm.com>
+Date: Fri, 18 Nov 2022 15:10:17 +0000
+Subject: [PATCH] arm64: dts: fvp: Add information about L1 and L2 caches
+
+Add the information about L1 and L2 caches on FVP RevC platform.
+Though the cache size is configurable through the model parameters,
+having default values in the device tree helps to exercise and debug
+any code utilising the cache information without the need of real
+hardware.
+
+Link: https://lore.kernel.org/r/20221118151017.704716-1-sudeep.holla@arm.com
+Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
+
+Signed-off-by: Jon Mason <jon.mason@arm.com>
+Upstream-Status: Backport
+---
+ arch/arm64/boot/dts/arm/fvp-base-revc.dts | 73 +++++++++++++++++++++++
+ 1 file changed, 73 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/arm/fvp-base-revc.dts b/arch/arm64/boot/dts/arm/fvp-base-revc.dts
+index 5f6f30c801a7..60472d65a355 100644
+--- a/arch/arm64/boot/dts/arm/fvp-base-revc.dts
+++ b/arch/arm64/boot/dts/arm/fvp-base-revc.dts
+@@ -47,48 +47,121 @@ cpu0: cpu@0 {
+ 			compatible = "arm,armv8";
+ 			reg = <0x0 0x000>;
+ 			enable-method = "psci";
+			i-cache-size = <0x8000>;
+			i-cache-line-size = <64>;
+			i-cache-sets = <256>;
+			d-cache-size = <0x8000>;
+			d-cache-line-size = <64>;
+			d-cache-sets = <256>;
+			next-level-cache = <&C0_L2>;
+ 		};
+ 		cpu1: cpu@100 {
+ 			device_type = "cpu";
+ 			compatible = "arm,armv8";
+ 			reg = <0x0 0x100>;
+ 			enable-method = "psci";
+			i-cache-size = <0x8000>;
+			i-cache-line-size = <64>;
+			i-cache-sets = <256>;
+			d-cache-size = <0x8000>;
+			d-cache-line-size = <64>;
+			d-cache-sets = <256>;
+			next-level-cache = <&C0_L2>;
+ 		};
+ 		cpu2: cpu@200 {
+ 			device_type = "cpu";
+ 			compatible = "arm,armv8";
+ 			reg = <0x0 0x200>;
+ 			enable-method = "psci";
+			i-cache-size = <0x8000>;
+			i-cache-line-size = <64>;
+			i-cache-sets = <256>;
+			d-cache-size = <0x8000>;
+			d-cache-line-size = <64>;
+			d-cache-sets = <256>;
+			next-level-cache = <&C0_L2>;
+ 		};
+ 		cpu3: cpu@300 {
+ 			device_type = "cpu";
+ 			compatible = "arm,armv8";
+ 			reg = <0x0 0x300>;
+ 			enable-method = "psci";
+			i-cache-size = <0x8000>;
+			i-cache-line-size = <64>;
+			i-cache-sets = <256>;
+			d-cache-size = <0x8000>;
+			d-cache-line-size = <64>;
+			d-cache-sets = <256>;
+			next-level-cache = <&C0_L2>;
+ 		};
+ 		cpu4: cpu@10000 {
+ 			device_type = "cpu";
+ 			compatible = "arm,armv8";
+ 			reg = <0x0 0x10000>;
+ 			enable-method = "psci";
+			i-cache-size = <0x8000>;
+			i-cache-line-size = <64>;
+			i-cache-sets = <256>;
+			d-cache-size = <0x8000>;
+			d-cache-line-size = <64>;
+			d-cache-sets = <256>;
+			next-level-cache = <&C1_L2>;
+ 		};
+ 		cpu5: cpu@10100 {
+ 			device_type = "cpu";
+ 			compatible = "arm,armv8";
+ 			reg = <0x0 0x10100>;
+ 			enable-method = "psci";
+			i-cache-size = <0x8000>;
+			i-cache-line-size = <64>;
+			i-cache-sets = <256>;
+			d-cache-size = <0x8000>;
+			d-cache-line-size = <64>;
+			d-cache-sets = <256>;
+			next-level-cache = <&C1_L2>;
+ 		};
+ 		cpu6: cpu@10200 {
+ 			device_type = "cpu";
+ 			compatible = "arm,armv8";
+ 			reg = <0x0 0x10200>;
+ 			enable-method = "psci";
+			i-cache-size = <0x8000>;
+			i-cache-line-size = <64>;
+			i-cache-sets = <256>;
+			d-cache-size = <0x8000>;
+			d-cache-line-size = <64>;
+			d-cache-sets = <256>;
+			next-level-cache = <&C1_L2>;
+ 		};
+ 		cpu7: cpu@10300 {
+ 			device_type = "cpu";
+ 			compatible = "arm,armv8";
+ 			reg = <0x0 0x10300>;
+ 			enable-method = "psci";
+			i-cache-size = <0x8000>;
+			i-cache-line-size = <64>;
+			i-cache-sets = <256>;
+			d-cache-size = <0x8000>;
+			d-cache-line-size = <64>;
+			d-cache-sets = <256>;
+			next-level-cache = <&C1_L2>;
+		};
+		C0_L2: l2-cache0 {
+			compatible = "cache";
+			cache-size = <0x80000>;
+			cache-line-size = <64>;
+			cache-sets = <512>;
+			cache-level = <2>;
+			cache-unified;
+		};
+
+		C1_L2: l2-cache1 {
+			compatible = "cache";
+			cache-size = <0x80000>;
+			cache-line-size = <64>;
+			cache-sets = <512>;
+			cache-level = <2>;
+			cache-unified;
+ 		};
+ 	};
+ 
@@ -0,0 +1,81 @@
+From 4edb625e2256d5761312110e34cbc0164915d772 Mon Sep 17 00:00:00 2001
+From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
+Date: Fri, 25 Nov 2022 15:41:12 +0100
+Subject: [PATCH] ARM: dts: vexpress: align LED node names with dtschema
+
+The node names should be generic and DT schema expects certain pattern.
+
+  vexpress-v2p-ca9.dtb: leds: 'user1', 'user2', 'user3', 'user4', 'user5', 'user6', 'user7', 'user8' do not match any of the regexes: '(^led-[0-9a-f]$|led)', 'pinctrl-[0-9]+'
+
+Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
+Link: https://lore.kernel.org/r/20221125144112.476817-1-krzysztof.kozlowski@linaro.org
+Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
+
+Signed-off-by: Jon Mason <jon.mason@arm.com>
+Upstream-Status: Backport
+---
+ arch/arm/boot/dts/vexpress-v2m.dtsi | 16 ++++++++--------
+ 1 file changed, 8 insertions(+), 8 deletions(-)
+
+diff --git a/arch/arm/boot/dts/vexpress-v2m.dtsi b/arch/arm/boot/dts/vexpress-v2m.dtsi
+index f434fe5cf4a1..def538ce8769 100644
+--- a/arch/arm/boot/dts/vexpress-v2m.dtsi
+++ b/arch/arm/boot/dts/vexpress-v2m.dtsi
+@@ -383,49 +383,49 @@ v2m_refclk32khz: refclk32khz {
+ 			leds {
+ 				compatible = "gpio-leds";
+ 
+-				user1 {
+				led-user1 {
+ 					label = "v2m:green:user1";
+ 					gpios = <&v2m_led_gpios 0 0>;
+ 					linux,default-trigger = "heartbeat";
+ 				};
+ 
+-				user2 {
+				led-user2 {
+ 					label = "v2m:green:user2";
+ 					gpios = <&v2m_led_gpios 1 0>;
+ 					linux,default-trigger = "mmc0";
+ 				};
+ 
+-				user3 {
+				led-user3 {
+ 					label = "v2m:green:user3";
+ 					gpios = <&v2m_led_gpios 2 0>;
+ 					linux,default-trigger = "cpu0";
+ 				};
+ 
+-				user4 {
+				led-user4 {
+ 					label = "v2m:green:user4";
+ 					gpios = <&v2m_led_gpios 3 0>;
+ 					linux,default-trigger = "cpu1";
+ 				};
+ 
+-				user5 {
+				led-user5 {
+ 					label = "v2m:green:user5";
+ 					gpios = <&v2m_led_gpios 4 0>;
+ 					linux,default-trigger = "cpu2";
+ 				};
+ 
+-				user6 {
+				led-user6 {
+ 					label = "v2m:green:user6";
+ 					gpios = <&v2m_led_gpios 5 0>;
+ 					linux,default-trigger = "cpu3";
+ 				};
+ 
+-				user7 {
+				led-user7 {
+ 					label = "v2m:green:user7";
+ 					gpios = <&v2m_led_gpios 6 0>;
+ 					linux,default-trigger = "cpu4";
+ 				};
+ 
+-				user8 {
+				led-user8 {
+ 					label = "v2m:green:user8";
+ 					gpios = <&v2m_led_gpios 7 0>;
+ 					linux,default-trigger = "cpu5";
@@ -0,0 +1,129 @@
+# Kernel configuration and dts specific information
+
+#
+# Kernel configurations and dts (If not using Linux provided ones) are captured
+# in this file. Update SRC_URI and do_patch for building images with custom dts
+#
+
+# We can't set FILESEXTRAPATHS once because of how the kernel classes search for
+# config fragments. Discussion is ongoing as to whether this is the correct
+# solution, or a workaround.
+# https://bugzilla.yoctoproject.org/show_bug.cgi?id=14154
+ARMBSPFILESPATHS := "${THISDIR}:${THISDIR}/files:"
+
+# Arm platforms kmeta
+SRC_URI_KMETA = "file://arm-platforms-kmeta;type=kmeta;name=arm-platforms-kmeta;destsuffix=arm-platforms-kmeta"
+SRC_URI:append:fvp-base = " ${SRC_URI_KMETA}"
+SRC_URI:append:fvp-baser-aemv8r64 = " ${SRC_URI_KMETA}"
+SRC_URI:append:juno = " ${SRC_URI_KMETA}"
+SRC_URI:append:n1sdp = " ${SRC_URI_KMETA}"
+SRCREV:arm-platforms-kmeta = "6147e82375aa9df8f2a162d42ea6406c79c854c5"
+
+#
+# Corstone-500 KMACHINE
+#
+COMPATIBLE_MACHINE:corstone500 = "corstone500"
+KBUILD_DEFCONFIG:corstone500  = "multi_v7_defconfig"
+KCONFIG_MODE:corstone500 = "--alldefconfig"
+
+#
+# Corstone1000 KMACHINE
+#
+FILESEXTRAPATHS:prepend:corstone1000 := "${ARMBSPFILESPATHS}"
+COMPATIBLE_MACHINE:corstone1000 = "${MACHINE}"
+KCONFIG_MODE:corstone1000 = "--alldefconfig"
+KMACHINE:corstone1000 = "corstone1000"
+LINUX_KERNEL_TYPE:corstone1000 = "standard"
+#disabling the rootfs cpio file compression so it is not compressed twice when bundled with the kernel
+KERNEL_EXTRA_ARGS:corstone1000 += "CONFIG_INITRAMFS_COMPRESSION_NONE=y"
+SRC_URI:append:corstone1000 = " \
+           file://defconfig  \
+           file://0002-Add-external-system-driver.patch \
+           file://0003-Add-rpmsg-driver-for-corstone1000.patch \
+           file://0004-rpmsg-arm-fix-return-value.patch \
+           file://0005-rpmsg-arm-update-chrdev-to-ctrldev-registration.patch \
+           file://0006-Adds-workaround-for-cs1k-specific-bug.patch \
+        "
+
+SRC_URI:append:corstone1000 = " ${@bb.utils.contains('MACHINE_FEATURES', \
+                                                            'corstone1000_kernel_debug', \
+                                                            'file://corstone1000_kernel_debug.cfg', \
+                                                            '', \
+                                                             d)}"
+
+# Default kernel features not needed for corstone1000
+# otherwise the extra kernel modules will increase the rootfs size
+# corstone1000 has limited flash memory constraints
+KERNEL_EXTRA_FEATURES:corstone1000 = ""
+KERNEL_FEATURES:corstone1000 = ""
+
+#
+# FVP BASE KMACHINE
+#
+COMPATIBLE_MACHINE:fvp-base = "fvp-base"
+KMACHINE:fvp-base = "fvp"
+FILESEXTRAPATHS:prepend:fvp-base := "${ARMBSPFILESPATHS}"
+SRC_URI:append:fvp-base = " file://0001-arm64-dts-fvp-Enable-virtio-rng-support.patch"
+
+#
+# FVP BaseR AEMv8r64 Machine
+#
+COMPATIBLE_MACHINE:fvp-baser-aemv8r64 = "fvp-baser-aemv8r64"
+FILESEXTRAPATHS:prepend:fvp-baser-aemv8r64 := "${ARMBSPFILESPATHS}"
+SRC_URI:append:fvp-baser-aemv8r64 = " file://fvp-baser-aemv8r64.dts;subdir=git/arch/arm64/boot/dts/arm"
+
+#
+# Juno KMACHINE
+#
+COMPATIBLE_MACHINE:juno = "juno"
+FILESEXTRAPATHS:prepend:juno := "${ARMBSPFILESPATHS}"
+SRC_URI:append:juno = " \
+    file://0001-arm64-dts-Update-cache-properties-for-Arm-Ltd-platfo.patch \
+    file://0002-arm64-dts-fvp-Add-SPE-to-Foundation-FVP.patch \
+    file://0003-arm64-dts-fvp-Add-information-about-L1-and-L2-caches.patch \
+    file://0004-ARM-dts-vexpress-align-LED-node-names-with-dtschema.patch \
+    "
+
+#
+# Musca B1/S2 can't run Linux
+#
+COMPATIBLE_MACHINE:musca-b1 = "(^$)"
+COMPATIBLE_MACHINE:musca-s1 = "(^$)"
+
+#
+# N1SDP KMACHINE
+#
+FILESEXTRAPATHS:prepend:n1sdp := "${THISDIR}/linux-yocto-6.1/n1sdp:"
+COMPATIBLE_MACHINE:n1sdp = "n1sdp"
+KBUILD_DEFCONFIG:n1sdp = "defconfig"
+KCONFIG_MODE:n1sdp = "--alldefconfig"
+FILESEXTRAPATHS:prepend:n1sdp := "${ARMBSPFILESPATHS}"
+SRC_URI:append:n1sdp = " \
+    file://0001-iommu-arm-smmu-v3-workaround-for-ATC_INV_SIZE_ALL-in.patch \
+    file://0002-n1sdp-pci_quirk-add-acs-override-for-PCI-devices.patch \
+    file://0003-pcie-Add-quirk-for-the-Arm-Neoverse-N1SDP-platform.patch \
+    file://0004-n1sdp-pcie-add-quirk-support-enabling-remote-chip-PC.patch \
+    file://0005-arm64-kpti-Whitelist-early-Arm-Neoverse-N1-revisions.patch \
+    file://0006-arm64-defconfig-disable-config-options-that-does-not.patch \
+    file://enable-nvme.cfg \
+    file://enable-realtek-R8169.cfg \
+    file://enable-usb_conn_gpio.cfg \
+    file://usb_xhci_pci_renesas.cfg \
+    "
+# Since we use the intree defconfig and the preempt-rt turns off some configs
+# do_kernel_configcheck will display warnings. So, lets disable it.
+KCONF_AUDIT_LEVEL:n1sdp:pn-linux-yocto-rt = "0"
+
+#
+# SGI575 KMACHINE
+#
+COMPATIBLE_MACHINE:sgi575 = "sgi575"
+KBUILD_DEFCONFIG:sgi575 = "defconfig"
+KCONFIG_MODE:sgi575 = "--alldefconfig"
+
+#
+# Total Compute (TC0/TC1) KMACHINE
+#
+COMPATIBLE_MACHINE:tc = "(tc0|tc1)"
+KBUILD_DEFCONFIG:tc = "defconfig"
+KCONFIG_MODE:tc = "--alldefconfig"
@@ -0,0 +1,47 @@
+From 32ae4539865e64bcfb0c6955bdac8db5904e493d Mon Sep 17 00:00:00 2001
+From: Manoj Kumar <manoj.kumar3@arm.com>
+Date: Mon, 1 Feb 2021 21:36:43 +0530
+Subject: [PATCH] iommu/arm-smmu-v3: workaround for ATC_INV_SIZE_ALL in N1SDP
+
+ATC_INV_SIZE_ALL request should automatically translate to ATS
+address which is not happening in SMMUv3 version gone into
+N1SDP platform. This workaround manually sets the ATS address
+field to proper value for ATC_INV_SIZE_ALL command.
+
+Change-Id: If89465be94720a62be85e1e6612f17e93fa9b8a5
+Signed-off-by: Manoj Kumar <manoj.kumar3@arm.com>
+Signed-off-by: Khasim Syed Mohammed <khasim.mohammed@arm.com>
+
+Upstream-Status: Inappropriate [Workaround]
+Signed-off-by: Manoj Kumar <manoj.kumar3@arm.com>
+Signed-off-by: Vishnu Banavath <vishnu.banavath@arm.com>
+Signed-off-by: Adam Johnston <adam.johnston@arm.com>
+---
+ drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 1 +
+ drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 1 +
+ 2 files changed, 2 insertions(+)
+
+diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c
+index d4d8bfee9feb..0524bf2ec021 100644
+--- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c
+++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c
+@@ -1738,6 +1738,7 @@ arm_smmu_atc_inv_to_cmd(int ssid, unsigned long iova, size_t size,
+ 	};
+ 
+ 	if (!size) {
+		cmd->atc.addr = ATC_INV_ADDR_ALL;
+ 		cmd->atc.size = ATC_INV_SIZE_ALL;
+ 		return;
+ 	}
+diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h
+index cd48590ada30..20892b2bfe1d 100644
+--- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h
+++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h
+@@ -472,6 +472,7 @@ struct arm_smmu_cmdq_ent {
+ 
+ 		#define CMDQ_OP_ATC_INV		0x40
+ 		#define ATC_INV_SIZE_ALL	52
+		#define ATC_INV_ADDR_ALL        0x7FFFFFFFFFFFF000UL
+ 		struct {
+ 			u32			sid;
+ 			u32			ssid;
@@ -0,0 +1,159 @@
+From fc8605e74b51d9e0ab8efd0489eca2e11d807f07 Mon Sep 17 00:00:00 2001
+From: Manoj Kumar <manoj.kumar3@arm.com>
+Date: Tue, 31 Aug 2021 16:15:38 +0000
+Subject: [PATCH] n1sdp: pci_quirk: add acs override for PCI devices
+
+Patch taken from:
+https://gitlab.com/Queuecumber/linux-acs-override/raw/master/workspaces/5.4/acso.patch
+
+Change-Id: Ib926bf50524ce9990fbaa2f2f8670fe84bd571f9
+Signed-off-by: Manoj Kumar <manoj.kumar3@arm.com>
+
+Upstream-Status: Inappropriate [will not be submitted as its a workaround to address hardware issue]
+Signed-off-by: Khasim Syed Mohammed <khasim.mohammed@arm.com>
+Signed-off-by: Vishnu Banavath <vishnu.banavath@arm.com>
+Signed-off-by: Adam Johnston <adam.johnston@arm.com>
+---
+ .../admin-guide/kernel-parameters.txt         |   8 ++
+ drivers/pci/quirks.c                          | 102 ++++++++++++++++++
+ 2 files changed, 110 insertions(+)
+
+diff --git a/Documentation/admin-guide/kernel-parameters.txt b/Documentation/admin-guide/kernel-parameters.txt
+index 963cdaecabcb..8e94af513b9f 100644
+--- a/Documentation/admin-guide/kernel-parameters.txt
+++ b/Documentation/admin-guide/kernel-parameters.txt
+@@ -4162,6 +4162,14 @@
+ 		nomsi		[MSI] If the PCI_MSI kernel config parameter is
+ 				enabled, this kernel boot option can be used to
+ 				disable the use of MSI interrupts system-wide.
+		pcie_acs_override [PCIE] Override missing PCIe ACS support for
+				downstream
+				All downstream ports - full ACS capabilities
+				multfunction
+				All multifunction devices - multifunction ACS subset
+				id:nnnn:nnnn
+				Specfic device - full ACS capabilities
+				Specified as vid:did (vendor/device ID) in hex
+ 		noioapicquirk	[APIC] Disable all boot interrupt quirks.
+ 				Safety option to keep boot IRQs enabled. This
+ 				should never be necessary.
+diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c
+index 285acc4aaccc..d6ebef1f30db 100644
+--- a/drivers/pci/quirks.c
+++ b/drivers/pci/quirks.c
+@@ -3612,6 +3612,107 @@ static void quirk_no_bus_reset(struct pci_dev *dev)
+ 	dev->dev_flags |= PCI_DEV_FLAGS_NO_BUS_RESET;
+ }
+ 
+static bool acs_on_downstream;
+static bool acs_on_multifunction;
+
+#define NUM_ACS_IDS 16
+struct acs_on_id {
+	unsigned short vendor;
+	unsigned short device;
+};
+static struct acs_on_id acs_on_ids[NUM_ACS_IDS];
+static u8 max_acs_id;
+
+static __init int pcie_acs_override_setup(char *p)
+{
+	if (!p)
+		return -EINVAL;
+
+	while (*p) {
+		if (!strncmp(p, "downstream", 10))
+			acs_on_downstream = true;
+		if (!strncmp(p, "multifunction", 13))
+			acs_on_multifunction = true;
+		if (!strncmp(p, "id:", 3)) {
+			char opt[5];
+			int ret;
+			long val;
+
+			if (max_acs_id >= NUM_ACS_IDS - 1) {
+				pr_warn("Out of PCIe ACS override slots (%d)\n",
+						NUM_ACS_IDS);
+				goto next;
+			}
+
+			p += 3;
+			snprintf(opt, 5, "%s", p);
+			ret = kstrtol(opt, 16, &val);
+			if (ret) {
+				pr_warn("PCIe ACS ID parse error %d\n", ret);
+				goto next;
+			}
+			acs_on_ids[max_acs_id].vendor = val;
+
+			p += strcspn(p, ":");
+			if (*p != ':') {
+				pr_warn("PCIe ACS invalid ID\n");
+				goto next;
+			}
+
+			p++;
+			snprintf(opt, 5, "%s", p);
+			ret = kstrtol(opt, 16, &val);
+			if (ret) {
+				pr_warn("PCIe ACS ID parse error %d\n", ret);
+				goto next;
+			}
+			acs_on_ids[max_acs_id].device = val;
+			max_acs_id++;
+		}
+next:
+		p += strcspn(p, ",");
+		if (*p == ',')
+			p++;
+	}
+
+	if (acs_on_downstream || acs_on_multifunction || max_acs_id)
+		pr_warn("Warning: PCIe ACS overrides enabled; This may allow non-IOMMU protected peer-to-peer DMA\n");
+
+	return 0;
+}
+early_param("pcie_acs_override", pcie_acs_override_setup);
+
+static int pcie_acs_overrides(struct pci_dev *dev, u16 acs_flags)
+{
+	int i;
+
+	/* Never override ACS for legacy devices or devices with ACS caps */
+	if (!pci_is_pcie(dev) ||
+		pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ACS))
+			return -ENOTTY;
+
+	for (i = 0; i < max_acs_id; i++)
+		if (acs_on_ids[i].vendor == dev->vendor &&
+			acs_on_ids[i].device == dev->device)
+				return 1;
+
+	switch (pci_pcie_type(dev)) {
+	case PCI_EXP_TYPE_DOWNSTREAM:
+	case PCI_EXP_TYPE_ROOT_PORT:
+		if (acs_on_downstream)
+			return 1;
+		break;
+	case PCI_EXP_TYPE_ENDPOINT:
+	case PCI_EXP_TYPE_UPSTREAM:
+	case PCI_EXP_TYPE_LEG_END:
+	case PCI_EXP_TYPE_RC_END:
+		if (acs_on_multifunction && dev->multifunction)
+			return 1;
+	}
+
+	return -ENOTTY;
+}
+
+ /*
+  * Some NVIDIA GPU devices do not work with bus reset, SBR needs to be
+  * prevented for those affected devices.
+@@ -4980,6 +5081,7 @@ static const struct pci_dev_acs_enabled {
+ 	{ PCI_VENDOR_ID_ZHAOXIN, PCI_ANY_ID, pci_quirk_zhaoxin_pcie_ports_acs },
+ 	/* Wangxun nics */
+ 	{ PCI_VENDOR_ID_WANGXUN, PCI_ANY_ID, pci_quirk_wangxun_nic_acs },
+	{ PCI_ANY_ID, PCI_ANY_ID, pcie_acs_overrides },
+ 	{ 0 }
+ };
+ 
@@ -0,0 +1,324 @@
+From 5aa5769af625c79589fd84b8afc06149c2362218 Mon Sep 17 00:00:00 2001
+From: Deepak Pandey <Deepak.Pandey@arm.com>
+Date: Fri, 31 May 2019 16:42:43 +0100
+Subject: [PATCH] pcie: Add quirk for the Arm Neoverse N1SDP platform
+
+The Arm N1SDP SoC suffers from some PCIe integration issues, most
+prominently config space accesses to not existing BDFs being answered
+with a bus abort, resulting in an SError.
+To mitigate this, the firmware scans the bus before boot (catching the
+SErrors) and creates a table with valid BDFs, which acts as a filter for
+Linux' config space accesses.
+
+Add code consulting the table as an ACPI PCIe quirk, also register the
+corresponding device tree based description of the host controller.
+Also fix the other two minor issues on the way, namely not being fully
+ECAM compliant and config space accesses being restricted to 32-bit
+accesses only.
+
+This allows the Arm Neoverse N1SDP board to boot Linux without crashing
+and to access *any* devices (there are no platform devices except UART).
+
+Signed-off-by: Deepak Pandey <Deepak.Pandey@arm.com>
+[Sudipto: extend to cover the CCIX root port as well]
+Signed-off-by: Sudipto Paul <sudipto.paul@arm.com>
+[Andre: fix coding style issues, rewrite some parts, add DT support]
+Signed-off-by: Andre Przywara <andre.przywara@arm.com>
+
+Change-Id: I1d3a4b9bf6b3b883d262e3c4ff1f88a0eb81c1fe
+Upstream-Status: Inappropriate [will not be submitted as its a workaround to address hardware issue]
+Signed-off-by: Deepak Pandey <Deepak.Pandey@arm.com>
+Signed-off-by: Vishnu Banavath <vishnu.banavath@arm.com>
+Signed-off-by: Adam Johnston <adam.johnston@arm.com>
+---
+ arch/arm64/configs/defconfig        |   1 +
+ drivers/acpi/pci_mcfg.c             |   7 +
+ drivers/pci/controller/Kconfig      |  11 ++
+ drivers/pci/controller/Makefile     |   2 +-
+ drivers/pci/controller/pcie-n1sdp.c | 198 ++++++++++++++++++++++++++++
+ include/linux/pci-ecam.h            |   2 +
+ 6 files changed, 220 insertions(+), 1 deletion(-)
+ create mode 100644 drivers/pci/controller/pcie-n1sdp.c
+
+diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
+index bbbc31391a65..973aa3b4d407 100644
+--- a/arch/arm64/configs/defconfig
+++ b/arch/arm64/configs/defconfig
+@@ -214,6 +214,7 @@ CONFIG_NFC_S3FWRN5_I2C=m
+ CONFIG_PCI=y
+ CONFIG_PCIEPORTBUS=y
+ CONFIG_PCIEAER=y
+CONFIG_PCI_QUIRKS=y
+ CONFIG_PCI_IOV=y
+ CONFIG_PCI_PASID=y
+ CONFIG_HOTPLUG_PCI=y
+diff --git a/drivers/acpi/pci_mcfg.c b/drivers/acpi/pci_mcfg.c
+index 860014b89b8e..2d4c1c699ffe 100644
+--- a/drivers/acpi/pci_mcfg.c
+++ b/drivers/acpi/pci_mcfg.c
+@@ -171,6 +171,13 @@ static struct mcfg_fixup mcfg_quirks[] = {
+ 	ALTRA_ECAM_QUIRK(1, 13),
+ 	ALTRA_ECAM_QUIRK(1, 14),
+ 	ALTRA_ECAM_QUIRK(1, 15),
+
+#define N1SDP_ECAM_MCFG(rev, seg, ops) \
+	{"ARMLTD", "ARMN1SDP", rev, seg, MCFG_BUS_ANY, ops }
+
+	/* N1SDP SoC with v1 PCIe controller */
+	N1SDP_ECAM_MCFG(0x20181101, 0, &pci_n1sdp_pcie_ecam_ops),
+	N1SDP_ECAM_MCFG(0x20181101, 1, &pci_n1sdp_ccix_ecam_ops),
+ #endif /* ARM64 */
+ 
+ #ifdef CONFIG_LOONGARCH
+diff --git a/drivers/pci/controller/Kconfig b/drivers/pci/controller/Kconfig
+index bfd9bac37e24..7a65799dded7 100644
+--- a/drivers/pci/controller/Kconfig
+++ b/drivers/pci/controller/Kconfig
+@@ -50,6 +50,17 @@ config PCI_IXP4XX
+ 	  Say Y here if you want support for the PCI host controller found
+ 	  in the Intel IXP4xx XScale-based network processor SoC.
+ 
+config PCIE_HOST_N1SDP_ECAM
+	bool "ARM N1SDP PCIe Controller"
+	depends on ARM64
+	depends on OF || (ACPI && PCI_QUIRKS)
+	select PCI_HOST_COMMON
+	default y if ARCH_VEXPRESS
+	help
+	  Say Y here if you want PCIe support for the Arm N1SDP platform.
+	  The controller is ECAM compliant, but needs a quirk to workaround
+	  an integration issue.
+
+ config PCI_TEGRA
+ 	bool "NVIDIA Tegra PCIe controller"
+ 	depends on ARCH_TEGRA || COMPILE_TEST
+diff --git a/drivers/pci/controller/Makefile b/drivers/pci/controller/Makefile
+index 37c8663de7fe..08e5afcf6e86 100644
+--- a/drivers/pci/controller/Makefile
+++ b/drivers/pci/controller/Makefile
+@@ -39,7 +39,7 @@ obj-$(CONFIG_PCI_LOONGSON) += pci-loongson.o
+ obj-$(CONFIG_PCIE_HISI_ERR) += pcie-hisi-error.o
+ obj-$(CONFIG_PCIE_APPLE) += pcie-apple.o
+ obj-$(CONFIG_PCIE_MT7621) += pcie-mt7621.o
+-
+obj-$(CONFIG_PCIE_HOST_N1SDP_ECAM) += pcie-n1sdp.o
+ # pcie-hisi.o quirks are needed even without CONFIG_PCIE_DW
+ obj-y				+= dwc/
+ obj-y				+= mobiveil/
+diff --git a/drivers/pci/controller/pcie-n1sdp.c b/drivers/pci/controller/pcie-n1sdp.c
+new file mode 100644
+index 000000000000..408699b9dcb1
+--- /dev/null
+++ b/drivers/pci/controller/pcie-n1sdp.c
+@@ -0,0 +1,198 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2018/2019 ARM Ltd.
+ *
+ * This quirk is to mask the following issues:
+ * - PCIE SLVERR: config space accesses to invalid PCIe BDFs cause a bus
+ *		  error (signalled as an asynchronous SError)
+ * - MCFG BDF mapping: the root complex is mapped separately from the device
+ *		       config space
+ * - Non 32-bit accesses to config space are not supported.
+ *
+ * At boot time the SCP board firmware creates a discovery table with
+ * the root complex' base address and the valid BDF values, discovered while
+ * scanning the config space and catching the SErrors.
+ * Linux responds only to the EPs listed in this table, returning NULL
+ * for the rest.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/ioport.h>
+#include <linux/sizes.h>
+#include <linux/of_pci.h>
+#include <linux/of.h>
+#include <linux/pci-ecam.h>
+#include <linux/platform_device.h>
+#include <linux/module.h>
+
+#include "../pci.h"
+
+/* Platform specific values as hardcoded in the firmware. */
+#define AP_NS_SHARED_MEM_BASE	0x06000000
+#define MAX_SEGMENTS		2		/* Two PCIe root complexes. */
+#define BDF_TABLE_SIZE		SZ_16K
+
+/*
+ * Shared memory layout as written by the SCP upon boot time:
+ *  ----
+ *  Discover data header --> RC base address
+ *                       \-> BDF Count
+ *  Discover data        --> BDF 0...n
+ *  ----
+ */
+struct pcie_discovery_data {
+	u32 rc_base_addr;
+	u32 nr_bdfs;
+	u32 valid_bdfs[0];
+} *pcie_discovery_data[MAX_SEGMENTS];
+
+void __iomem *rc_remapped_addr[MAX_SEGMENTS];
+
+/*
+ * map_bus() is called before we do a config space access for a certain
+ * device. We use this to check whether this device is valid, avoiding
+ * config space accesses which would result in an SError otherwise.
+ */
+static void __iomem *pci_n1sdp_map_bus(struct pci_bus *bus, unsigned int devfn,
+				       int where)
+{
+	struct pci_config_window *cfg = bus->sysdata;
+	unsigned int devfn_shift = cfg->ops->bus_shift - 8;
+	unsigned int busn = bus->number;
+	unsigned int segment = bus->domain_nr;
+	unsigned int bdf_addr;
+	unsigned int table_count, i;
+	struct pci_dev *dev;
+
+	if (segment >= MAX_SEGMENTS ||
+	    busn < cfg->busr.start || busn > cfg->busr.end)
+		return NULL;
+
+	/* The PCIe root complex has a separate config space mapping. */
+	if (busn == 0 && devfn == 0)
+		return rc_remapped_addr[segment] + where;
+
+	dev = pci_get_domain_bus_and_slot(segment, busn, devfn);
+	if (dev && dev->is_virtfn)
+		return pci_ecam_map_bus(bus, devfn, where);
+
+	/* Accesses beyond the vendor ID always go to existing devices. */
+	if (where > 0)
+		return pci_ecam_map_bus(bus, devfn, where);
+
+	busn -= cfg->busr.start;
+	bdf_addr = (busn << cfg->ops->bus_shift) + (devfn << devfn_shift);
+	table_count = pcie_discovery_data[segment]->nr_bdfs;
+	for (i = 0; i < table_count; i++) {
+		if (bdf_addr == pcie_discovery_data[segment]->valid_bdfs[i])
+			return pci_ecam_map_bus(bus, devfn, where);
+	}
+
+	return NULL;
+}
+
+static int pci_n1sdp_init(struct pci_config_window *cfg, unsigned int segment)
+{
+	phys_addr_t table_base;
+	struct device *dev = cfg->parent;
+	struct pcie_discovery_data *shared_data;
+	size_t bdfs_size;
+
+	if (segment >= MAX_SEGMENTS)
+		return -ENODEV;
+
+	table_base = AP_NS_SHARED_MEM_BASE + segment * BDF_TABLE_SIZE;
+
+	if (!request_mem_region(table_base, BDF_TABLE_SIZE,
+				"PCIe valid BDFs")) {
+		dev_err(dev, "PCIe BDF shared region request failed\n");
+		return -ENOMEM;
+	}
+
+	shared_data = devm_ioremap(dev,
+				   table_base, BDF_TABLE_SIZE);
+	if (!shared_data)
+		return -ENOMEM;
+
+	/* Copy the valid BDFs structure to allocated normal memory. */
+	bdfs_size = sizeof(struct pcie_discovery_data) +
+		    sizeof(u32) * shared_data->nr_bdfs;
+	pcie_discovery_data[segment] = devm_kmalloc(dev, bdfs_size, GFP_KERNEL);
+	if (!pcie_discovery_data[segment])
+		return -ENOMEM;
+
+	memcpy_fromio(pcie_discovery_data[segment], shared_data, bdfs_size);
+
+	rc_remapped_addr[segment] = devm_ioremap(dev,
+						 shared_data->rc_base_addr,
+						 PCI_CFG_SPACE_EXP_SIZE);
+	if (!rc_remapped_addr[segment]) {
+		dev_err(dev, "Cannot remap root port base\n");
+		return -ENOMEM;
+	}
+
+	devm_iounmap(dev, shared_data);
+
+	return 0;
+}
+
+/* Called for ACPI segment 0, and for all segments when using DT. */
+static int pci_n1sdp_pcie_init(struct pci_config_window *cfg)
+{
+	struct platform_device *pdev = to_platform_device(cfg->parent);
+	int segment = 0;
+
+	if (pdev->dev.of_node)
+		segment = of_get_pci_domain_nr(pdev->dev.of_node);
+	if (segment < 0 || segment > MAX_SEGMENTS) {
+		dev_err(&pdev->dev, "N1SDP PCI controllers require linux,pci-domain property\n");
+		dev_err(&pdev->dev, "Or invalid segment number, must be smaller than %d\n",
+			MAX_SEGMENTS);
+		return -EINVAL;
+	}
+
+	return pci_n1sdp_init(cfg, segment);
+}
+
+/* Called for ACPI segment 1. */
+static int pci_n1sdp_ccix_init(struct pci_config_window *cfg)
+{
+	return pci_n1sdp_init(cfg, 1);
+}
+
+const struct pci_ecam_ops pci_n1sdp_pcie_ecam_ops = {
+	.bus_shift	= 20,
+	.init		= pci_n1sdp_pcie_init,
+	.pci_ops	= {
+		.map_bus        = pci_n1sdp_map_bus,
+		.read           = pci_generic_config_read32,
+		.write          = pci_generic_config_write32,
+	}
+};
+
+const struct pci_ecam_ops pci_n1sdp_ccix_ecam_ops = {
+	.bus_shift	= 20,
+	.init		= pci_n1sdp_ccix_init,
+	.pci_ops	= {
+		.map_bus        = pci_n1sdp_map_bus,
+		.read           = pci_generic_config_read32,
+		.write          = pci_generic_config_write32,
+	}
+};
+
+static const struct of_device_id n1sdp_pcie_of_match[] = {
+	{ .compatible = "arm,n1sdp-pcie", .data = &pci_n1sdp_pcie_ecam_ops },
+	{ },
+};
+MODULE_DEVICE_TABLE(of, n1sdp_pcie_of_match);
+
+static struct platform_driver n1sdp_pcie_driver = {
+	.driver = {
+		.name = KBUILD_MODNAME,
+		.of_match_table = n1sdp_pcie_of_match,
+		.suppress_bind_attrs = true,
+	},
+	.probe = pci_host_common_probe,
+};
+builtin_platform_driver(n1sdp_pcie_driver);
+diff --git a/include/linux/pci-ecam.h b/include/linux/pci-ecam.h
+index 6b1301e2498e..b3cf3adeab28 100644
+--- a/include/linux/pci-ecam.h
+++ b/include/linux/pci-ecam.h
+@@ -88,6 +88,8 @@ extern const struct pci_ecam_ops xgene_v2_pcie_ecam_ops; /* APM X-Gene PCIe v2.x
+ extern const struct pci_ecam_ops al_pcie_ops;	/* Amazon Annapurna Labs PCIe */
+ extern const struct pci_ecam_ops tegra194_pcie_ops; /* Tegra194 PCIe */
+ extern const struct pci_ecam_ops loongson_pci_ecam_ops; /* Loongson PCIe */
+extern const struct pci_ecam_ops pci_n1sdp_pcie_ecam_ops; /* Arm N1SDP PCIe */
+extern const struct pci_ecam_ops pci_n1sdp_ccix_ecam_ops; /* Arm N1SDP PCIe */
+ #endif
+ 
+ #if IS_ENABLED(CONFIG_PCI_HOST_COMMON)
@@ -0,0 +1,136 @@
+From b59e0d6c6035db80fc9044df0333f96ede53ad7a Mon Sep 17 00:00:00 2001
+From: Sayanta Pattanayak <sayanta.pattanayak@arm.com>
+Date: Wed, 9 Feb 2022 20:37:43 +0530
+Subject: [PATCH] n1sdp: pcie: add quirk support enabling remote chip PCIe
+
+Base address mapping for remote chip Root PCIe ECAM space.
+
+When two N1SDP boards are coupled via the CCIX connection, the PCI host
+complex of the remote board appears as PCIe segment 2 on the primary board.
+The resources of the secondary board, including the host complex, are
+mapped at offset 0x40000000000 into the address space of the primary
+board, so take that into account when accessing the remote PCIe segment.
+
+Change-Id: I0e8d1eb119aef6444b9df854a39b24441c12195a
+Signed-off-by: Sayanta Pattanayak <sayanta.pattanayak@arm.com>
+Signed-off-by: Khasim Syed Mohammed <khasim.mohammed@arm.com>
+Signed-off-by: Andre Przywara <andre.przywara@arm.com>
+Signed-off-by: sahil <sahil@arm.com>
+
+Upstream-Status: Inappropriate [will not be submitted as its an hack required to fix the hardware issue]
+Signed-off-by: Sayanta Pattanayak <sayanta.pattanayak@arm.com>
+Signed-off-by: Vishnu Banavath <vishnu.banavath@arm.com>
+Signed-off-by: Adam Johnston <adam.johnston@arm.com>
+---
+ drivers/acpi/pci_mcfg.c             |  1 +
+ drivers/pci/controller/pcie-n1sdp.c | 32 +++++++++++++++++++++++++----
+ include/linux/pci-ecam.h            |  1 +
+ 3 files changed, 30 insertions(+), 4 deletions(-)
+
+diff --git a/drivers/acpi/pci_mcfg.c b/drivers/acpi/pci_mcfg.c
+index 2d4c1c699ffe..27f1e9a45c17 100644
+--- a/drivers/acpi/pci_mcfg.c
+++ b/drivers/acpi/pci_mcfg.c
+@@ -178,6 +178,7 @@ static struct mcfg_fixup mcfg_quirks[] = {
+ 	/* N1SDP SoC with v1 PCIe controller */
+ 	N1SDP_ECAM_MCFG(0x20181101, 0, &pci_n1sdp_pcie_ecam_ops),
+ 	N1SDP_ECAM_MCFG(0x20181101, 1, &pci_n1sdp_ccix_ecam_ops),
+	N1SDP_ECAM_MCFG(0x20181101, 2, &pci_n1sdp_remote_pcie_ecam_ops),
+ #endif /* ARM64 */
+ 
+ #ifdef CONFIG_LOONGARCH
+diff --git a/drivers/pci/controller/pcie-n1sdp.c b/drivers/pci/controller/pcie-n1sdp.c
+index 408699b9dcb1..b3b02417fd7d 100644
+--- a/drivers/pci/controller/pcie-n1sdp.c
+++ b/drivers/pci/controller/pcie-n1sdp.c
+@@ -30,8 +30,10 @@
+ 
+ /* Platform specific values as hardcoded in the firmware. */
+ #define AP_NS_SHARED_MEM_BASE	0x06000000
+-#define MAX_SEGMENTS		2		/* Two PCIe root complexes. */
+/* Two PCIe root complexes in One Chip + One PCIe RC in Remote Chip */
+#define MAX_SEGMENTS		3
+ #define BDF_TABLE_SIZE		SZ_16K
+#define REMOTE_CHIP_ADDR_OFFSET	0x40000000000
+ 
+ /*
+  * Shared memory layout as written by the SCP upon boot time:
+@@ -97,12 +99,17 @@ static int pci_n1sdp_init(struct pci_config_window *cfg, unsigned int segment)
+ 	phys_addr_t table_base;
+ 	struct device *dev = cfg->parent;
+ 	struct pcie_discovery_data *shared_data;
+-	size_t bdfs_size;
+	size_t bdfs_size, rc_base_addr = 0;
+ 
+ 	if (segment >= MAX_SEGMENTS)
+ 		return -ENODEV;
+ 
+-	table_base = AP_NS_SHARED_MEM_BASE + segment * BDF_TABLE_SIZE;
+	if (segment > 1) {
+		rc_base_addr = REMOTE_CHIP_ADDR_OFFSET;
+		table_base = AP_NS_SHARED_MEM_BASE + REMOTE_CHIP_ADDR_OFFSET;
+	} else {
+		table_base = AP_NS_SHARED_MEM_BASE + segment * BDF_TABLE_SIZE;
+	}
+ 
+ 	if (!request_mem_region(table_base, BDF_TABLE_SIZE,
+ 				"PCIe valid BDFs")) {
+@@ -114,6 +121,7 @@ static int pci_n1sdp_init(struct pci_config_window *cfg, unsigned int segment)
+ 				   table_base, BDF_TABLE_SIZE);
+ 	if (!shared_data)
+ 		return -ENOMEM;
+	rc_base_addr += shared_data->rc_base_addr;
+ 
+ 	/* Copy the valid BDFs structure to allocated normal memory. */
+ 	bdfs_size = sizeof(struct pcie_discovery_data) +
+@@ -125,7 +133,7 @@ static int pci_n1sdp_init(struct pci_config_window *cfg, unsigned int segment)
+ 	memcpy_fromio(pcie_discovery_data[segment], shared_data, bdfs_size);
+ 
+ 	rc_remapped_addr[segment] = devm_ioremap(dev,
+-						 shared_data->rc_base_addr,
+						 rc_base_addr,
+ 						 PCI_CFG_SPACE_EXP_SIZE);
+ 	if (!rc_remapped_addr[segment]) {
+ 		dev_err(dev, "Cannot remap root port base\n");
+@@ -161,6 +169,12 @@ static int pci_n1sdp_ccix_init(struct pci_config_window *cfg)
+ 	return pci_n1sdp_init(cfg, 1);
+ }
+ 
+/* Called for ACPI segment 2. */
+static int pci_n1sdp_remote_pcie_init(struct pci_config_window *cfg)
+{
+	return pci_n1sdp_init(cfg, 2);
+}
+
+ const struct pci_ecam_ops pci_n1sdp_pcie_ecam_ops = {
+ 	.bus_shift	= 20,
+ 	.init		= pci_n1sdp_pcie_init,
+@@ -181,6 +195,16 @@ const struct pci_ecam_ops pci_n1sdp_ccix_ecam_ops = {
+ 	}
+ };
+ 
+const struct pci_ecam_ops pci_n1sdp_remote_pcie_ecam_ops = {
+	.bus_shift	= 20,
+	.init		= pci_n1sdp_remote_pcie_init,
+	.pci_ops	= {
+		.map_bus        = pci_n1sdp_map_bus,
+		.read           = pci_generic_config_read32,
+		.write          = pci_generic_config_write32,
+	}
+};
+
+ static const struct of_device_id n1sdp_pcie_of_match[] = {
+ 	{ .compatible = "arm,n1sdp-pcie", .data = &pci_n1sdp_pcie_ecam_ops },
+ 	{ },
+diff --git a/include/linux/pci-ecam.h b/include/linux/pci-ecam.h
+index b3cf3adeab28..d4316795c00d 100644
+--- a/include/linux/pci-ecam.h
+++ b/include/linux/pci-ecam.h
+@@ -90,6 +90,7 @@ extern const struct pci_ecam_ops tegra194_pcie_ops; /* Tegra194 PCIe */
+ extern const struct pci_ecam_ops loongson_pci_ecam_ops; /* Loongson PCIe */
+ extern const struct pci_ecam_ops pci_n1sdp_pcie_ecam_ops; /* Arm N1SDP PCIe */
+ extern const struct pci_ecam_ops pci_n1sdp_ccix_ecam_ops; /* Arm N1SDP PCIe */
+extern const struct pci_ecam_ops pci_n1sdp_remote_pcie_ecam_ops; /* Arm N1SDP PCIe */
+ #endif
+ 
+ #if IS_ENABLED(CONFIG_PCI_HOST_COMMON)
@@ -0,0 +1,33 @@
+From ff02f77788f8c01e9d675912c063e89415804b7d Mon Sep 17 00:00:00 2001
+From: Andre Przywara <andre.przywara@arm.com>
+Date: Fri, 17 May 2019 17:39:27 +0100
+Subject: [PATCH] arm64: kpti: Whitelist early Arm Neoverse N1 revisions
+
+Early revisions (r1p0) of the Neoverse N1 core did not feature the
+CSV3 field in ID_AA64PFR0_EL1 to advertise they are not affected by
+the Spectre variant 3 (aka Meltdown) vulnerability.
+
+Add this particular revision to the whitelist to avoid enabling KPTI.
+
+Signed-off-by: Andre Przywara <andre.przywara@arm.com>
+Change-Id: I78df055a3e674aefd195d41cc6dc4ee08b0af099
+Upstream-Status: Inappropriate
+Signed-off-by: Andre Przywara <andre.przywara@arm.com>
+Signed-off-by: Vishnu Banavath <vishnu.banavath@arm.com>
+Signed-off-by: Adam Johnston <adam.johnston@arm.com>
+---
+ arch/arm64/kernel/cpufeature.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c
+index b3f37e2209ad..b74210f38cd8 100644
+--- a/arch/arm64/kernel/cpufeature.c
+++ b/arch/arm64/kernel/cpufeature.c
+@@ -1646,6 +1646,7 @@ static bool unmap_kernel_at_el0(const struct arm64_cpu_capabilities *entry,
+ 		MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_2XX_SILVER),
+ 		MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_3XX_SILVER),
+ 		MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_4XX_SILVER),
+		MIDR_REV(MIDR_NEOVERSE_N1, 1, 0),	/* missing CSV3 */
+ 		{ /* sentinel */ }
+ 	};
+ 	char const *str = "kpti command line option";
@@ -0,0 +1,39 @@
+From 330a620b5c73505e62a2e0accc155fbc78859cee Mon Sep 17 00:00:00 2001
+From: Vishnu Banavath <vishnu.banavath@arm.com>
+Date: Wed, 21 Sep 2022 15:54:14 +0100
+Subject: [PATCH] arm64: defconfig: disable config options that does not apply
+ anymore
+
+Following config options should be not set to be more accurate and
+works with build system like yocto
+CONFIG_BT_HCIUART_MRVL
+CONFIG_BT_MRVL
+CONFIG_BT_MRVL_SDIO
+CONFIG_BT_QCOMSMD
+
+Upstream-Status: Pending [not submitted upstream yet]
+Signed-off-by: Adam Johnston <adam.johnston@arm.com>
+Signed-off-by: Vishnu Banavath <vishnu.banavath@arm.com>
+---
+ arch/arm64/configs/defconfig | 8 ++++----
+ 1 file changed, 4 insertions(+), 4 deletions(-)
+
+diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
+index 973aa3b4d407..61f040394a2d 100644
+--- a/arch/arm64/configs/defconfig
+++ b/arch/arm64/configs/defconfig
+@@ -198,10 +198,10 @@ CONFIG_BT_HCIUART=m
+ CONFIG_BT_HCIUART_LL=y
+ CONFIG_BT_HCIUART_BCM=y
+ CONFIG_BT_HCIUART_QCA=y
+-CONFIG_BT_HCIUART_MRVL=y
+-CONFIG_BT_MRVL=m
+-CONFIG_BT_MRVL_SDIO=m
+-CONFIG_BT_QCOMSMD=m
+# CONFIG_BT_HCIUART_MRVL is not set
+# CONFIG_BT_MRVL is not set
+# CONFIG_BT_MRVL_SDIO is not set
+# CONFIG_BT_QCOMSMD is not set
+ CONFIG_CFG80211=m
+ CONFIG_MAC80211=m
+ CONFIG_MAC80211_LEDS=y
@@ -0,0 +1,3 @@
+# Enable NVMe flash storage support
+CONFIG_NVME_CORE=y
+CONFIG_BLK_DEV_NVME=y
@@ -0,0 +1,3 @@
+# Enable Realtek Gigabit Ethernet adapter
+CONFIG_REALTEK_PHY=y
+CONFIG_R8169=y
@@ -0,0 +1,2 @@
+# PHY_TEGRA_XUSB sets this to y, but its set as m in defconfig
+CONFIG_USB_CONN_GPIO=y
@@ -0,0 +1,2 @@
+# CONFIG_USB_XHCI_PCI is not set
+# CONFIG_USB_XHCI_PCI_RENESAS is not set
@@ -0,0 +1,6 @@
+# Only enable linux-yocto-rt for n1sdp and the Armv8-R AArch64 AEM FVP
+LINUX_YOCTO_RT_REQUIRE ?= ""
+LINUX_YOCTO_RT_REQUIRE:n1sdp = "linux-arm-platforms.inc"
+LINUX_YOCTO_RT_REQUIRE:fvp-baser-aemv8r64 = "linux-arm-platforms.inc"
+
+require ${LINUX_YOCTO_RT_REQUIRE}
@@ -0,0 +1,3 @@
+# Add support for Arm Platforms (boards or simulators)
+
+require linux-arm-platforms.inc