Your Name
137 lines
5.4 KiB
Diff
137 lines
5.4 KiB
Diff
From b59e0d6c6035db80fc9044df0333f96ede53ad7a Mon Sep 17 00:00:00 2001
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From: Sayanta Pattanayak <sayanta.pattanayak@arm.com>
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Date: Wed, 9 Feb 2022 20:37:43 +0530
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Subject: [PATCH] n1sdp: pcie: add quirk support enabling remote chip PCIe
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Base address mapping for remote chip Root PCIe ECAM space.
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When two N1SDP boards are coupled via the CCIX connection, the PCI host
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complex of the remote board appears as PCIe segment 2 on the primary board.
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The resources of the secondary board, including the host complex, are
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mapped at offset 0x40000000000 into the address space of the primary
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board, so take that into account when accessing the remote PCIe segment.
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Change-Id: I0e8d1eb119aef6444b9df854a39b24441c12195a
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Signed-off-by: Sayanta Pattanayak <sayanta.pattanayak@arm.com>
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Signed-off-by: Khasim Syed Mohammed <khasim.mohammed@arm.com>
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Signed-off-by: Andre Przywara <andre.przywara@arm.com>
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Signed-off-by: sahil <sahil@arm.com>
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Upstream-Status: Inappropriate [will not be submitted as its an hack required to fix the hardware issue]
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Signed-off-by: Sayanta Pattanayak <sayanta.pattanayak@arm.com>
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Signed-off-by: Vishnu Banavath <vishnu.banavath@arm.com>
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Signed-off-by: Adam Johnston <adam.johnston@arm.com>
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---
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drivers/acpi/pci_mcfg.c | 1 +
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drivers/pci/controller/pcie-n1sdp.c | 32 +++++++++++++++++++++++++----
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include/linux/pci-ecam.h | 1 +
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3 files changed, 30 insertions(+), 4 deletions(-)
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diff --git a/drivers/acpi/pci_mcfg.c b/drivers/acpi/pci_mcfg.c
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index 2d4c1c699ffe..27f1e9a45c17 100644
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--- a/drivers/acpi/pci_mcfg.c
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+++ b/drivers/acpi/pci_mcfg.c
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@@ -178,6 +178,7 @@ static struct mcfg_fixup mcfg_quirks[] = {
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/* N1SDP SoC with v1 PCIe controller */
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N1SDP_ECAM_MCFG(0x20181101, 0, &pci_n1sdp_pcie_ecam_ops),
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N1SDP_ECAM_MCFG(0x20181101, 1, &pci_n1sdp_ccix_ecam_ops),
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+ N1SDP_ECAM_MCFG(0x20181101, 2, &pci_n1sdp_remote_pcie_ecam_ops),
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#endif /* ARM64 */
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#ifdef CONFIG_LOONGARCH
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diff --git a/drivers/pci/controller/pcie-n1sdp.c b/drivers/pci/controller/pcie-n1sdp.c
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index 408699b9dcb1..b3b02417fd7d 100644
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--- a/drivers/pci/controller/pcie-n1sdp.c
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+++ b/drivers/pci/controller/pcie-n1sdp.c
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@@ -30,8 +30,10 @@
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/* Platform specific values as hardcoded in the firmware. */
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#define AP_NS_SHARED_MEM_BASE 0x06000000
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-#define MAX_SEGMENTS 2 /* Two PCIe root complexes. */
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+/* Two PCIe root complexes in One Chip + One PCIe RC in Remote Chip */
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+#define MAX_SEGMENTS 3
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#define BDF_TABLE_SIZE SZ_16K
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+#define REMOTE_CHIP_ADDR_OFFSET 0x40000000000
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/*
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* Shared memory layout as written by the SCP upon boot time:
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@@ -97,12 +99,17 @@ static int pci_n1sdp_init(struct pci_config_window *cfg, unsigned int segment)
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phys_addr_t table_base;
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struct device *dev = cfg->parent;
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struct pcie_discovery_data *shared_data;
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- size_t bdfs_size;
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+ size_t bdfs_size, rc_base_addr = 0;
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if (segment >= MAX_SEGMENTS)
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return -ENODEV;
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- table_base = AP_NS_SHARED_MEM_BASE + segment * BDF_TABLE_SIZE;
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+ if (segment > 1) {
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+ rc_base_addr = REMOTE_CHIP_ADDR_OFFSET;
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+ table_base = AP_NS_SHARED_MEM_BASE + REMOTE_CHIP_ADDR_OFFSET;
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+ } else {
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+ table_base = AP_NS_SHARED_MEM_BASE + segment * BDF_TABLE_SIZE;
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+ }
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if (!request_mem_region(table_base, BDF_TABLE_SIZE,
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"PCIe valid BDFs")) {
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@@ -114,6 +121,7 @@ static int pci_n1sdp_init(struct pci_config_window *cfg, unsigned int segment)
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table_base, BDF_TABLE_SIZE);
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if (!shared_data)
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return -ENOMEM;
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+ rc_base_addr += shared_data->rc_base_addr;
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/* Copy the valid BDFs structure to allocated normal memory. */
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bdfs_size = sizeof(struct pcie_discovery_data) +
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@@ -125,7 +133,7 @@ static int pci_n1sdp_init(struct pci_config_window *cfg, unsigned int segment)
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memcpy_fromio(pcie_discovery_data[segment], shared_data, bdfs_size);
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rc_remapped_addr[segment] = devm_ioremap(dev,
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- shared_data->rc_base_addr,
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+ rc_base_addr,
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PCI_CFG_SPACE_EXP_SIZE);
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if (!rc_remapped_addr[segment]) {
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dev_err(dev, "Cannot remap root port base\n");
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@@ -161,6 +169,12 @@ static int pci_n1sdp_ccix_init(struct pci_config_window *cfg)
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return pci_n1sdp_init(cfg, 1);
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}
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+/* Called for ACPI segment 2. */
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+static int pci_n1sdp_remote_pcie_init(struct pci_config_window *cfg)
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+{
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+ return pci_n1sdp_init(cfg, 2);
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+}
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+
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const struct pci_ecam_ops pci_n1sdp_pcie_ecam_ops = {
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.bus_shift = 20,
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.init = pci_n1sdp_pcie_init,
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@@ -181,6 +195,16 @@ const struct pci_ecam_ops pci_n1sdp_ccix_ecam_ops = {
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}
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};
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+const struct pci_ecam_ops pci_n1sdp_remote_pcie_ecam_ops = {
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+ .bus_shift = 20,
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+ .init = pci_n1sdp_remote_pcie_init,
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+ .pci_ops = {
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+ .map_bus = pci_n1sdp_map_bus,
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+ .read = pci_generic_config_read32,
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+ .write = pci_generic_config_write32,
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+ }
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+};
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+
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static const struct of_device_id n1sdp_pcie_of_match[] = {
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{ .compatible = "arm,n1sdp-pcie", .data = &pci_n1sdp_pcie_ecam_ops },
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{ },
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diff --git a/include/linux/pci-ecam.h b/include/linux/pci-ecam.h
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index b3cf3adeab28..d4316795c00d 100644
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--- a/include/linux/pci-ecam.h
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+++ b/include/linux/pci-ecam.h
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@@ -90,6 +90,7 @@ extern const struct pci_ecam_ops tegra194_pcie_ops; /* Tegra194 PCIe */
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extern const struct pci_ecam_ops loongson_pci_ecam_ops; /* Loongson PCIe */
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extern const struct pci_ecam_ops pci_n1sdp_pcie_ecam_ops; /* Arm N1SDP PCIe */
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extern const struct pci_ecam_ops pci_n1sdp_ccix_ecam_ops; /* Arm N1SDP PCIe */
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+extern const struct pci_ecam_ops pci_n1sdp_remote_pcie_ecam_ops; /* Arm N1SDP PCIe */
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#endif
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#if IS_ENABLED(CONFIG_PCI_HOST_COMMON)
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