Your Name
158 lines
4.7 KiB
Diff
158 lines
4.7 KiB
Diff
From 97a8ca1835f5d9512dacda497540d5523e56c7dd Mon Sep 17 00:00:00 2001
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From: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com>
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Date: Tue, 26 Apr 2022 14:43:58 +0100
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Subject: [PATCH] feat: emulate interrupt controller register access
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This emulates ICC_SGI1R_EL1 and ICC_IGRPEN1_EL1 register
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Signed-off-by: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com>
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Change-Id: I0c11f034f3676067597461a183a341c809adcaa4
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Upstream-Status: Inappropriate [Experimental feature]
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---
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src/arch/aarch64/hypervisor/handler.c | 5 ++
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src/arch/aarch64/hypervisor/perfmon.c | 84 +++++++++++++++++++++++++++
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src/arch/aarch64/hypervisor/perfmon.h | 5 ++
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src/arch/aarch64/msr.h | 3 +
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4 files changed, 97 insertions(+)
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diff --git a/src/arch/aarch64/hypervisor/handler.c b/src/arch/aarch64/hypervisor/handler.c
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index 4c1b6e48..cd5146bd 100644
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--- a/src/arch/aarch64/hypervisor/handler.c
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+++ b/src/arch/aarch64/hypervisor/handler.c
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@@ -1283,6 +1283,11 @@ void handle_system_register_access(uintreg_t esr_el2)
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inject_el1_unknown_exception(vcpu, esr_el2);
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return;
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}
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+ } else if (intr_ctrl_is_register_access(esr_el2)) {
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+ if (!intr_ctrl_el1_process_access(vcpu, vm_id, esr_el2)) {
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+ inject_el1_unknown_exception(vcpu, esr_el2);
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+ return;
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+ }
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} else {
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inject_el1_unknown_exception(vcpu, esr_el2);
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return;
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diff --git a/src/arch/aarch64/hypervisor/perfmon.c b/src/arch/aarch64/hypervisor/perfmon.c
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index f13b0354..05e216c8 100644
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--- a/src/arch/aarch64/hypervisor/perfmon.c
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+++ b/src/arch/aarch64/hypervisor/perfmon.c
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@@ -116,6 +116,10 @@
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X(PMEVTYPER30_EL0 , 3, 3, 14, 15, 6) \
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X(PMCCFILTR_EL0 , 3, 3, 14, 15, 7)
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+#define INTR_CTRL_REGISTERS \
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+ X(ICC_IGRPEN1_EL1 , 3, 0, 12, 12, 7) \
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+ X(ICC_SGI1R_EL1 , 3, 0, 12, 11, 5) \
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+
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/* clang-format on */
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/**
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@@ -232,3 +236,83 @@ uintreg_t perfmon_get_pmccfiltr_el0_init_value(ffa_vm_id_t vm_id)
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return 0;
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}
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+
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+bool intr_ctrl_is_register_access(uintreg_t esr)
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+{
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+ uintreg_t op0 = GET_ISS_OP0(esr);
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+ uintreg_t op1 = GET_ISS_OP1(esr);
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+ uintreg_t crn = GET_ISS_CRN(esr);
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+ uintreg_t crm = GET_ISS_CRM(esr);
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+
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+ if (op0 == 3 && op1 == 0 && crn == 12 && crm == 12) {
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+ return true;
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+ }
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+
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+ if (op0 == 3 && op1 == 0 && crn == 12 && crm == 11) {
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+ return true;
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+ }
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+
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+ return false;
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+}
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+
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+bool intr_ctrl_el1_process_access(struct vcpu *vcpu, ffa_vm_id_t vm_id,
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+ uintreg_t esr)
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+{
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+ uintreg_t sys_register = GET_ISS_SYSREG(esr);
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+ uintreg_t rt_register = GET_ISS_RT(esr);
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+ uintreg_t value;
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+
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+ /* +1 because Rt can access register XZR */
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+ CHECK(rt_register < NUM_GP_REGS + 1);
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+
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+ if (ISS_IS_READ(esr)) {
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+ switch (sys_register) {
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+#define X(reg_name, op0, op1, crn, crm, op2) \
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+ case (GET_ISS_ENCODING(op0, op1, crn, crm, op2)): \
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+ value = read_msr(reg_name); \
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+ break;
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+ INTR_CTRL_REGISTERS
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+#undef X
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+ default:
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+ value = vcpu->regs.r[rt_register];
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+ dlog_notice(
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+ "Unsupported interrupt control register "
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+ "read: "
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+ "op0=%d, op1=%d, crn=%d, crm=%d, op2=%d, "
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+ "rt=%d.\n",
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+ GET_ISS_OP0(esr), GET_ISS_OP1(esr),
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+ GET_ISS_CRN(esr), GET_ISS_CRM(esr),
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+ GET_ISS_OP2(esr), GET_ISS_RT(esr));
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+ break;
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+ }
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+ if (rt_register != RT_REG_XZR) {
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+ vcpu->regs.r[rt_register] = value;
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+ }
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+ } else {
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+ if (rt_register != RT_REG_XZR) {
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+ value = vcpu->regs.r[rt_register];
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+ } else {
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+ value = 0;
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+ }
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+ switch (sys_register) {
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+#define X(reg_name, op0, op1, crn, crm, op2) \
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+ case (GET_ISS_ENCODING(op0, op1, crn, crm, op2)): \
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+ write_msr(reg_name, value); \
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+ break;
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+ INTR_CTRL_REGISTERS
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+#undef X
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+ default:
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+ dlog_notice(
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+ "Unsupported interrupt control register "
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+ "write: "
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+ "op0=%d, op1=%d, crn=%d, crm=%d, op2=%d, "
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+ "rt=%d.\n",
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+ GET_ISS_OP0(esr), GET_ISS_OP1(esr),
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+ GET_ISS_CRN(esr), GET_ISS_CRM(esr),
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+ GET_ISS_OP2(esr), GET_ISS_RT(esr));
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+ break;
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+ }
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+ }
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+
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+ return true;
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+}
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diff --git a/src/arch/aarch64/hypervisor/perfmon.h b/src/arch/aarch64/hypervisor/perfmon.h
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index 81669ba1..c90d45bf 100644
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--- a/src/arch/aarch64/hypervisor/perfmon.h
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+++ b/src/arch/aarch64/hypervisor/perfmon.h
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@@ -70,3 +70,8 @@ bool perfmon_process_access(struct vcpu *vcpu, ffa_vm_id_t vm_id,
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uintreg_t esr_el2);
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uintreg_t perfmon_get_pmccfiltr_el0_init_value(ffa_vm_id_t vm_id);
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+
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+bool intr_ctrl_is_register_access(uintreg_t esr);
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+
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+bool intr_ctrl_el1_process_access(struct vcpu *vcpu, ffa_vm_id_t vm_id,
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+ uintreg_t esr);
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diff --git a/src/arch/aarch64/msr.h b/src/arch/aarch64/msr.h
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index 55e78330..82aa8846 100644
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--- a/src/arch/aarch64/msr.h
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+++ b/src/arch/aarch64/msr.h
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@@ -134,3 +134,6 @@
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#define MSR_CNTHPS_CTL_EL2 S3_4_C14_C5_1
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#define MSR_CNTHPS_CVAL_EL2 S3_4_C14_C5_2
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#define MSR_CNTHPS_TVAL_EL2 S3_4_C14_C5_0
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+
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+#define ICC_IGRPEN1_EL1 S3_0_C12_C12_7
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+#define ICC_SGI1R_EL1 S3_0_C12_C11_5
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