Your Name
50 lines
1.6 KiB
Diff
50 lines
1.6 KiB
Diff
From fa73d885be85eee4369b292ec601e7b024a68807 Mon Sep 17 00:00:00 2001
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From: Jaxson Han <jaxson.han@arm.com>
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Date: Tue, 2 Nov 2021 10:48:39 +0800
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Subject: [PATCH] PSCI: Apply flush cache after setting branch_data
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For v8-R64, Hypervisor calls boot-wrapper's PSCI service using simple
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function call (instead of hvc).
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In this case, hypervisor's main core has enabled MPU and cache, but
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the secondary cores which are spinning have not enabled cache.
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That means if the main core set the branch_data to 1 to boot other
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cores, the secondary cores cannot see the change of branch_data and
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also cannot break the spin.
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Thus, the PSCI service in boot-wrapper needs a cache flush after
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setting branch_data in order to let other cores see the change.
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Issue-ID: SCM-3816
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Upstream-Status: Inappropriate [other]
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Implementation pending further discussion
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Signed-off-by: Jaxson Han <jaxson.han@arm.com>
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Change-Id: Ifc282091c54d8fb2ffdb8cfa7fd3ffc1f4be717e
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---
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common/psci.c | 6 ++++++
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1 file changed, 6 insertions(+)
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diff --git a/common/psci.c b/common/psci.c
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index 945780b..6efc695 100644
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--- a/common/psci.c
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+++ b/common/psci.c
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@@ -24,12 +24,18 @@ static unsigned long branch_table[NR_CPUS];
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bakery_ticket_t branch_table_lock[NR_CPUS];
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+static inline void flush_per_cpu_data(void *data)
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+{
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+ asm volatile ("dc cvac, %0" : : "r" (data));
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+}
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+
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static int psci_store_address(unsigned int cpu, unsigned long address)
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{
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if (branch_table[cpu] != PSCI_ADDR_INVALID)
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return PSCI_RET_ALREADY_ON;
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branch_table[cpu] = address;
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+ flush_per_cpu_data((void*)&(branch_table[cpu]));
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return PSCI_RET_SUCCESS;
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}
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