Your Name
61 lines
1.7 KiB
Diff
61 lines
1.7 KiB
Diff
From 3cd9aa92ab8ddd230cf6a9a68a27a18705b6f57c Mon Sep 17 00:00:00 2001
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From: Xo Wang <xow@google.com>
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Date: Thu, 20 Oct 2016 16:26:29 -0700
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Subject: [PATCH 1/2] board/aspeed: Add reset_phy() for Zaius
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The Broadcom PHY for the Zaius BMC requires a hard reset after RGMII
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clocks are enabled. Add reset_phy() implementation and configure it to
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be called.
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Signed-off-by: Xo Wang <xow@google.com>
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---
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board/aspeed/ast-g5/ast-g5.c | 19 +++++++++++++++++++
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include/configs/ast-common.h | 3 +++
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2 files changed, 22 insertions(+)
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diff --git a/board/aspeed/ast-g5/ast-g5.c b/board/aspeed/ast-g5/ast-g5.c
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index da79d7b..433ad18 100644
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--- a/board/aspeed/ast-g5/ast-g5.c
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+++ b/board/aspeed/ast-g5/ast-g5.c
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@@ -33,6 +33,25 @@ int dram_init(void)
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return 0;
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}
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+void reset_phy(void)
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+{
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+ unsigned long reg;
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+ /* D3 in GPIOA/B/C/D direction and data registers */
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+ unsigned long phy_reset_mask = BIT(27);
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+
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+ /* Assert MAC2 PHY hardware reset */
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+ /* Set pin low */
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+ reg = readl(AST_GPIO_BASE | 0x00);
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+ writel(reg & ~phy_reset_mask, AST_GPIO_BASE | 0x00);
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+ /* Enable pin for output */
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+ reg = readl(AST_GPIO_BASE | 0x04);
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+ writel(reg | phy_reset_mask, AST_GPIO_BASE | 0x04);
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+ udelay(3);
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+ /* Set pin high */
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+ reg = readl(AST_GPIO_BASE | 0x00);
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+ writel(reg | phy_reset_mask, AST_GPIO_BASE | 0x00);
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+}
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+
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#ifdef CONFIG_FTGMAC100
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int board_eth_init(bd_t *bd)
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{
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diff --git a/include/configs/ast-common.h b/include/configs/ast-common.h
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index b39ea33..3566f73 100644
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--- a/include/configs/ast-common.h
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+++ b/include/configs/ast-common.h
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@@ -104,4 +104,7 @@
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"spi_dma=yes\0" \
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""
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+/* Call reset_phy() */
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+#define CONFIG_RESET_PHY_R 1
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+
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#endif /* __AST_COMMON_CONFIG_H */
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--
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2.8.0.rc3.226.g39d4020
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