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147 lines
4.0 KiB
Diff
147 lines
4.0 KiB
Diff
From 22e740d069e14875a64864bf86e0826a96560b44 Mon Sep 17 00:00:00 2001
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From: Sudeep Holla <sudeep.holla@arm.com>
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Date: Fri, 18 Nov 2022 15:10:17 +0000
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Subject: [PATCH] arm64: dts: fvp: Add information about L1 and L2 caches
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Add the information about L1 and L2 caches on FVP RevC platform.
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Though the cache size is configurable through the model parameters,
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having default values in the device tree helps to exercise and debug
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any code utilising the cache information without the need of real
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hardware.
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Link: https://lore.kernel.org/r/20221118151017.704716-1-sudeep.holla@arm.com
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Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
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Signed-off-by: Jon Mason <jon.mason@arm.com>
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Upstream-Status: Backport
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---
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arch/arm64/boot/dts/arm/fvp-base-revc.dts | 73 +++++++++++++++++++++++
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1 file changed, 73 insertions(+)
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diff --git a/arch/arm64/boot/dts/arm/fvp-base-revc.dts b/arch/arm64/boot/dts/arm/fvp-base-revc.dts
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index 5f6f30c801a7..60472d65a355 100644
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--- a/arch/arm64/boot/dts/arm/fvp-base-revc.dts
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+++ b/arch/arm64/boot/dts/arm/fvp-base-revc.dts
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@@ -47,48 +47,121 @@ cpu0: cpu@0 {
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compatible = "arm,armv8";
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reg = <0x0 0x000>;
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enable-method = "psci";
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+ i-cache-size = <0x8000>;
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+ i-cache-line-size = <64>;
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+ i-cache-sets = <256>;
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+ d-cache-size = <0x8000>;
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+ d-cache-line-size = <64>;
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+ d-cache-sets = <256>;
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+ next-level-cache = <&C0_L2>;
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};
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cpu1: cpu@100 {
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device_type = "cpu";
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compatible = "arm,armv8";
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reg = <0x0 0x100>;
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enable-method = "psci";
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+ i-cache-size = <0x8000>;
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+ i-cache-line-size = <64>;
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+ i-cache-sets = <256>;
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+ d-cache-size = <0x8000>;
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+ d-cache-line-size = <64>;
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+ d-cache-sets = <256>;
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+ next-level-cache = <&C0_L2>;
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};
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cpu2: cpu@200 {
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device_type = "cpu";
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compatible = "arm,armv8";
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reg = <0x0 0x200>;
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enable-method = "psci";
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+ i-cache-size = <0x8000>;
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+ i-cache-line-size = <64>;
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+ i-cache-sets = <256>;
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+ d-cache-size = <0x8000>;
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+ d-cache-line-size = <64>;
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+ d-cache-sets = <256>;
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+ next-level-cache = <&C0_L2>;
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};
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cpu3: cpu@300 {
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device_type = "cpu";
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compatible = "arm,armv8";
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reg = <0x0 0x300>;
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enable-method = "psci";
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+ i-cache-size = <0x8000>;
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+ i-cache-line-size = <64>;
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+ i-cache-sets = <256>;
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+ d-cache-size = <0x8000>;
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+ d-cache-line-size = <64>;
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+ d-cache-sets = <256>;
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+ next-level-cache = <&C0_L2>;
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};
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cpu4: cpu@10000 {
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device_type = "cpu";
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compatible = "arm,armv8";
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reg = <0x0 0x10000>;
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enable-method = "psci";
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+ i-cache-size = <0x8000>;
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+ i-cache-line-size = <64>;
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+ i-cache-sets = <256>;
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+ d-cache-size = <0x8000>;
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+ d-cache-line-size = <64>;
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+ d-cache-sets = <256>;
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+ next-level-cache = <&C1_L2>;
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};
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cpu5: cpu@10100 {
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device_type = "cpu";
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compatible = "arm,armv8";
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reg = <0x0 0x10100>;
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enable-method = "psci";
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+ i-cache-size = <0x8000>;
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+ i-cache-line-size = <64>;
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+ i-cache-sets = <256>;
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+ d-cache-size = <0x8000>;
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+ d-cache-line-size = <64>;
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+ d-cache-sets = <256>;
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+ next-level-cache = <&C1_L2>;
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};
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cpu6: cpu@10200 {
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device_type = "cpu";
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compatible = "arm,armv8";
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reg = <0x0 0x10200>;
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enable-method = "psci";
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+ i-cache-size = <0x8000>;
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+ i-cache-line-size = <64>;
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+ i-cache-sets = <256>;
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+ d-cache-size = <0x8000>;
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+ d-cache-line-size = <64>;
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+ d-cache-sets = <256>;
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+ next-level-cache = <&C1_L2>;
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};
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cpu7: cpu@10300 {
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device_type = "cpu";
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compatible = "arm,armv8";
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reg = <0x0 0x10300>;
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enable-method = "psci";
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+ i-cache-size = <0x8000>;
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+ i-cache-line-size = <64>;
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+ i-cache-sets = <256>;
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+ d-cache-size = <0x8000>;
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+ d-cache-line-size = <64>;
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+ d-cache-sets = <256>;
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+ next-level-cache = <&C1_L2>;
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+ };
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+ C0_L2: l2-cache0 {
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+ compatible = "cache";
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+ cache-size = <0x80000>;
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+ cache-line-size = <64>;
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+ cache-sets = <512>;
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+ cache-level = <2>;
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+ cache-unified;
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+ };
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+
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+ C1_L2: l2-cache1 {
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+ compatible = "cache";
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+ cache-size = <0x80000>;
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+ cache-line-size = <64>;
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+ cache-sets = <512>;
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+ cache-level = <2>;
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+ cache-unified;
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};
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};
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