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139 lines
4.5 KiB
Diff
139 lines
4.5 KiB
Diff
From dc250cab31c6611cc7fa76bc8b2027dbd56dd65d Mon Sep 17 00:00:00 2001
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From: Pierre Gondois <pierre.gondois@arm.com>
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Date: Mon, 7 Nov 2022 16:56:58 +0100
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Subject: [PATCH] arm64: dts: Update cache properties for Arm Ltd platforms
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The DeviceTree Specification v0.3 specifies that the cache node
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"compatible" and "cache-level" properties are required.
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Cf. s3.8 Multi-level and Shared Cache Nodes
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The 'cache-unified' property should be present if one of the properties
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for unified cache is present ('cache-size', ...).
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Update the relevant device trees nodes accordingly.
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Signed-off-by: Pierre Gondois <pierre.gondois@arm.com>
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Link: https://lore.kernel.org/r/20221107155825.1644604-6-pierre.gondois@arm.com
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Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
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Signed-off-by: Jon Mason <jon.mason@arm.com>
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Upstream-Status: Backport
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---
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arch/arm64/boot/dts/arm/corstone1000.dtsi | 1 +
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arch/arm64/boot/dts/arm/foundation-v8.dtsi | 1 +
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arch/arm64/boot/dts/arm/juno-r1.dts | 2 ++
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arch/arm64/boot/dts/arm/juno-r2.dts | 2 ++
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arch/arm64/boot/dts/arm/juno.dts | 2 ++
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arch/arm64/boot/dts/arm/rtsm_ve-aemv8a.dts | 1 +
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arch/arm64/boot/dts/arm/vexpress-v2f-1xv7-ca53x2.dts | 1 +
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7 files changed, 10 insertions(+)
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diff --git a/arch/arm64/boot/dts/arm/corstone1000.dtsi b/arch/arm64/boot/dts/arm/corstone1000.dtsi
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index 4e46826f883a..21f1f952e985 100644
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--- a/arch/arm64/boot/dts/arm/corstone1000.dtsi
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+++ b/arch/arm64/boot/dts/arm/corstone1000.dtsi
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@@ -53,6 +53,7 @@ gic: interrupt-controller@1c000000 {
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L2_0: l2-cache0 {
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compatible = "cache";
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+ cache-unified;
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cache-level = <2>;
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cache-size = <0x80000>;
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cache-line-size = <64>;
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diff --git a/arch/arm64/boot/dts/arm/foundation-v8.dtsi b/arch/arm64/boot/dts/arm/foundation-v8.dtsi
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index 83e3e7e3984f..c8bd23b1a7ba 100644
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--- a/arch/arm64/boot/dts/arm/foundation-v8.dtsi
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+++ b/arch/arm64/boot/dts/arm/foundation-v8.dtsi
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@@ -58,6 +58,7 @@ cpu3: cpu@3 {
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L2_0: l2-cache0 {
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compatible = "cache";
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+ cache-level = <2>;
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};
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};
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diff --git a/arch/arm64/boot/dts/arm/juno-r1.dts b/arch/arm64/boot/dts/arm/juno-r1.dts
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index 6451c62146fd..1d90eeebb37d 100644
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--- a/arch/arm64/boot/dts/arm/juno-r1.dts
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+++ b/arch/arm64/boot/dts/arm/juno-r1.dts
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@@ -189,6 +189,7 @@ A53_3: cpu@103 {
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A57_L2: l2-cache0 {
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compatible = "cache";
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+ cache-unified;
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cache-size = <0x200000>;
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cache-line-size = <64>;
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cache-sets = <2048>;
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@@ -197,6 +198,7 @@ A57_L2: l2-cache0 {
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A53_L2: l2-cache1 {
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compatible = "cache";
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+ cache-unified;
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cache-size = <0x100000>;
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cache-line-size = <64>;
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cache-sets = <1024>;
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diff --git a/arch/arm64/boot/dts/arm/juno-r2.dts b/arch/arm64/boot/dts/arm/juno-r2.dts
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index 438cd1ff4bd0..d2ada69b0a43 100644
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--- a/arch/arm64/boot/dts/arm/juno-r2.dts
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+++ b/arch/arm64/boot/dts/arm/juno-r2.dts
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@@ -195,6 +195,7 @@ A53_3: cpu@103 {
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A72_L2: l2-cache0 {
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compatible = "cache";
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+ cache-unified;
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cache-size = <0x200000>;
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cache-line-size = <64>;
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cache-sets = <2048>;
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@@ -203,6 +204,7 @@ A72_L2: l2-cache0 {
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A53_L2: l2-cache1 {
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compatible = "cache";
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+ cache-unified;
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cache-size = <0x100000>;
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cache-line-size = <64>;
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cache-sets = <1024>;
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diff --git a/arch/arm64/boot/dts/arm/juno.dts b/arch/arm64/boot/dts/arm/juno.dts
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index cf4a58211399..5e48a01a5b9f 100644
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--- a/arch/arm64/boot/dts/arm/juno.dts
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+++ b/arch/arm64/boot/dts/arm/juno.dts
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@@ -194,6 +194,7 @@ A53_3: cpu@103 {
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A57_L2: l2-cache0 {
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compatible = "cache";
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+ cache-unified;
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cache-size = <0x200000>;
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cache-line-size = <64>;
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cache-sets = <2048>;
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@@ -202,6 +203,7 @@ A57_L2: l2-cache0 {
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A53_L2: l2-cache1 {
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compatible = "cache";
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+ cache-unified;
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cache-size = <0x100000>;
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cache-line-size = <64>;
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cache-sets = <1024>;
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diff --git a/arch/arm64/boot/dts/arm/rtsm_ve-aemv8a.dts b/arch/arm64/boot/dts/arm/rtsm_ve-aemv8a.dts
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index 258991ad7cc0..ef68f5aae7dd 100644
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--- a/arch/arm64/boot/dts/arm/rtsm_ve-aemv8a.dts
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+++ b/arch/arm64/boot/dts/arm/rtsm_ve-aemv8a.dts
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@@ -71,6 +71,7 @@ cpu@3 {
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L2_0: l2-cache0 {
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compatible = "cache";
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+ cache-level = <2>;
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};
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};
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diff --git a/arch/arm64/boot/dts/arm/vexpress-v2f-1xv7-ca53x2.dts b/arch/arm64/boot/dts/arm/vexpress-v2f-1xv7-ca53x2.dts
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index 5b6d9d8e934d..796cd7d02eb5 100644
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--- a/arch/arm64/boot/dts/arm/vexpress-v2f-1xv7-ca53x2.dts
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+++ b/arch/arm64/boot/dts/arm/vexpress-v2f-1xv7-ca53x2.dts
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@@ -57,6 +57,7 @@ cpu@1 {
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L2_0: l2-cache0 {
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compatible = "cache";
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+ cache-level = <2>;
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};
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};
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