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2026-04-23 17:07:55 +08:00
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meta-phosphor/dynamic-layers/aspeed-layer/recipes-bsp/u-boot/files/0001-aspeed-Disable-unnecessary-features.patch
+278
View File
@@ -0,0 +1,278 @@
From 97566253f336d85d23abef777b54dc572ca7ac9a Mon Sep 17 00:00:00 2001
From: Andrew Jeffery <andrew@aj.id.au>
Date: Mon, 23 Jul 2018 15:22:34 +0930
Subject: [PATCH] aspeed: Disable unnecessary features
Adjust board_init() to disable hardware features that we don't need
available during normal BMC operation.
Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
---
arch/arm/include/asm/arch-aspeed/regs-lpc.h | 29 +++++++++++
arch/arm/include/asm/arch-aspeed/regs-scu.h | 8 ++-
arch/arm/include/asm/arch-aspeed/regs-sdmc.h | 17 +++++++
board/aspeed/ast-g4/ast-g4.c | 46 ++++++++++++++++-
board/aspeed/ast-g5/ast-g5.c | 52 +++++++++++++++++++-
5 files changed, 149 insertions(+), 3 deletions(-)
create mode 100644 arch/arm/include/asm/arch-aspeed/regs-lpc.h
diff --git a/arch/arm/include/asm/arch-aspeed/regs-lpc.h b/arch/arm/include/asm/arch-aspeed/regs-lpc.h
new file mode 100644
index 000000000000..b0162ae4f37c
--- /dev/null
+++ b/arch/arm/include/asm/arch-aspeed/regs-lpc.h
@@ -0,0 +1,29 @@
+/* arch/arm/mach-aspeed/include/mach/regs-sdmc.h
+ *
+ * Copyright (C) 2018 IBM Corp
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * History :
+ * 1. 2018/07/23 Andrew Jeffery Create
+ *
+ ******************************************************************************/
+#ifndef __AST_REGS_LPC_H
+#define __AST_REGS_LPC_H
+
+/*
+ * Register for LPC
+ */
+
+#define AST_LPC_HICR5 0x80
+#define AST_LPC_HICRB 0x100
+
+/* AST_LPC_HICR5 : 0x80 Host Interface Control Register 5 */
+#define LPC_HICR5_ENFWH (0x1 << 10)
+
+/* AST_LPC_HICRB : 0x100 Host Interface Control Register B */
+#define LPC_HICRB_ILPC2AHB (0x1 << 6)
+
+#endif
diff --git a/arch/arm/include/asm/arch-aspeed/regs-scu.h b/arch/arm/include/asm/arch-aspeed/regs-scu.h
index b714fa92341d..c9b91795d1aa 100644
--- a/arch/arm/include/asm/arch-aspeed/regs-scu.h
+++ b/arch/arm/include/asm/arch-aspeed/regs-scu.h
@@ -466,6 +466,7 @@
#define SCU_MISC_JTAG__M_TO_PCIE_EN (0x1 << 14)
#define SCU_MISC_VUART_TO_CTRL (0x1 << 13)
#define SCU_MISC_DIV13_EN (0x1 << 12)
+#define SCU_MISC_DEBUG_UART (0x1 << 10)
#define SCU_MISC_Y_CLK_INVERT (0x1 << 11)
#define SCU_MISC_OUT_DELAY (0x1 << 9)
#define SCU_MISC_PCI_TO_AHB_DIS (0x1 << 8)
@@ -548,6 +549,7 @@
/* AST_SCU_VGA_SCRATCH7 0x6c - VGA Scratch register */
/* AST_SCU_HW_STRAP1 0x70 - hardware strapping register */
+#define SCU_HW_STRAP_LPC_DEC_SUPER_IO (0x1 << 20)
#ifdef AST_SOC_G5
#define CLK_25M_IN (0x1 << 23)
@@ -593,7 +595,6 @@
#define SCU_HW_STRAP_GPIOE_PT_EN (0x1 << 22)
#define SCU_HW_STRAP_GPIOD_PT_EN (0x1 << 21)
-#define SCU_HW_STRAP_LPC_DEC_SUPER_IO (0x1 << 20)
#define SCU_HW_STRAP_ACPI_DIS (0x1 << 19)
/* bit 23, 18 [1,0] */
@@ -940,6 +941,11 @@
/* AST_SCU_UART24_REF 0x160 - Generate UART 24Mhz Ref from H-PLL when CLKIN is 25Mhz */
/* AST_SCU_PCIE_CONFIG_SET 0x180 - PCI-E Configuration Setting Control Register */
+#define SCU_PCIE_CONFIG_SET_BMC_DMA (0x1 << 14)
+#define SCU_PCIE_CONFIG_SET_BMC_MMIO (0x1 << 9)
+#define SCU_PCIE_CONFIG_SET_BMC_EN (0x1 << 8)
+#define SCU_PCIE_CONFIG_SET_VGA_MMIO (0x1 << 1)
+
/* AST_SCU_BMC_MMIO_DEC 0x184 - BMC MMIO Decode Setting Register */
/* AST_SCU_DEC_AREA1 0x188 - 1st relocated controller decode area location */
/* AST_SCU_DEC_AREA2 0x18C - 2nd relocated controller decode area location */
diff --git a/arch/arm/include/asm/arch-aspeed/regs-sdmc.h b/arch/arm/include/asm/arch-aspeed/regs-sdmc.h
index 2cc26d29aa9e..2773d3c19e5a 100644
--- a/arch/arm/include/asm/arch-aspeed/regs-sdmc.h
+++ b/arch/arm/include/asm/arch-aspeed/regs-sdmc.h
@@ -13,11 +13,14 @@
#ifndef __AST_REGS_SDMC_H
#define __AST_REGS_SDMC_H
+#include <asm/arch/aspeed.h>
+
/*
* Register for SDMC
*/
#define AST_SDMC_PROTECT 0x00 /* protection key register */
#define AST_SDMC_CONFIG 0x04 /* Configuration register */
+#define AST_SDMC_GFX_PROT 0x08 /* Graphics protection register */
/* AST_SDMC_PROTECT: 0x00 - protection key register */
#define SDMC_PROTECT_UNLOCK 0xFC600309
@@ -29,4 +32,18 @@
#define SDMC_CONFIG_CACHE_EN (0x1 << 10)
#define SDMC_CONFIG_EEC_EN (0x1 << 7)
+/* AST_SDMC_GFX_PROT : 0x08 - Graphics protection register */
+#define SDMC_GFX_PROT_VGA_CURSOR (0x1 << 0)
+#define SDMC_GFX_PROT_VGA_CG_READ (0x1 << 1)
+#define SDMC_GFX_PROT_VGA_ASCII_READ (0x1 << 2)
+#define SDMC_GFX_PROT_VGA_CRT (0x1 << 3)
+
+#if defined(AST_SOC_G5)
+#define SDMC_GFX_PROT_PCIE (0x1 << 16)
+#define SDMC_GFX_PROT_XDMA (0x1 << 17)
+#elif defined(AST_SOC_G4)
+#define SDMC_GFX_PROT_PCIE (0x1 << 10)
+#define SDMC_GFX_PROT_XDMA (0x1 << 16)
+#endif
+
#endif
diff --git a/board/aspeed/ast-g4/ast-g4.c b/board/aspeed/ast-g4/ast-g4.c
index 656495307b03..5b137e7d74bc 100644
--- a/board/aspeed/ast-g4/ast-g4.c
+++ b/board/aspeed/ast-g4/ast-g4.c
@@ -1,6 +1,6 @@
/*
* (C) Copyright 2002 Ryan Chen
- * Copyright 2016 IBM Corporation
+ * Copyright 2016,2018 IBM Corporation
*
* SPDX-License-Identifier: GPL-2.0+
*/
@@ -12,13 +12,57 @@
#include <asm/arch/ast-sdmc.h>
#include <asm/arch/ast_scu.h>
#include <asm/arch/regs-ahbc.h>
+#include <asm/arch/regs-lpc.h>
#include <asm/arch/regs-scu.h>
+#include <asm/arch/regs-sdmc.h>
#include <asm/io.h>
DECLARE_GLOBAL_DATA_PTR;
int board_init(void)
{
+ bool sdmc_unlocked;
+ u32 val;
+
+ /* iLPC2AHB */
+ val = readl(AST_SCU_BASE + AST_SCU_HW_STRAP1);
+ val |= SCU_HW_STRAP_LPC_DEC_SUPER_IO;
+ writel(val, AST_SCU_BASE + AST_SCU_HW_STRAP1);
+
+ val = readl(AST_LPC_BASE + AST_LPC_HICRB);
+ val |= LPC_HICRB_ILPC2AHB;
+ writel(val, AST_LPC_BASE + AST_LPC_HICRB);
+
+ /* P2A, PCIe BMC */
+ val = readl(AST_SCU_BASE + AST_SCU_PCIE_CONFIG_SET);
+ val &= ~(SCU_PCIE_CONFIG_SET_BMC_DMA
+ | SCU_PCIE_CONFIG_SET_BMC_MMIO
+ | SCU_PCIE_CONFIG_SET_BMC_EN
+ | SCU_PCIE_CONFIG_SET_VGA_MMIO);
+ writel(val, AST_SCU_BASE + AST_SCU_PCIE_CONFIG_SET);
+
+ /* X-DMA */
+ sdmc_unlocked = readl(AST_SDMC_BASE + AST_SDMC_PROTECT);
+ if (!sdmc_unlocked)
+ writel(SDMC_PROTECT_UNLOCK, AST_SDMC_BASE + AST_SDMC_PROTECT);
+
+ val = readl(AST_SDMC_BASE + AST_SDMC_GFX_PROT);
+ val |= (SDMC_GFX_PROT_VGA_CURSOR
+ | SDMC_GFX_PROT_VGA_CG_READ
+ | SDMC_GFX_PROT_VGA_ASCII_READ
+ | SDMC_GFX_PROT_VGA_CRT
+ | SDMC_GFX_PROT_PCIE
+ | SDMC_GFX_PROT_XDMA);
+ writel(val, AST_SDMC_BASE + AST_SDMC_GFX_PROT);
+
+ if (!sdmc_unlocked)
+ writel(~SDMC_PROTECT_UNLOCK, AST_SDMC_BASE + AST_SDMC_PROTECT);
+
+ /* LPC2AHB */
+ val = readl(AST_LPC_BASE + AST_LPC_HICR5);
+ val &= ~LPC_HICR5_ENFWH;
+ writel(val, AST_LPC_BASE + AST_LPC_HICR5);
+
/* address of boot parameters */
gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
gd->flags = 0;
diff --git a/board/aspeed/ast-g5/ast-g5.c b/board/aspeed/ast-g5/ast-g5.c
index e67a4bf8b2b4..12496cea09b7 100644
--- a/board/aspeed/ast-g5/ast-g5.c
+++ b/board/aspeed/ast-g5/ast-g5.c
@@ -1,5 +1,5 @@
/*
- * Copyright 2016 IBM Corporation
+ * Copyright 2016,2018 IBM Corporation
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
@@ -12,12 +12,62 @@
#include <asm/arch/ast_scu.h>
#include <asm/arch/ast-sdmc.h>
+#include <asm/arch/regs-lpc.h>
+#include <asm/arch/regs-scu.h>
+#include <asm/arch/regs-sdmc.h>
#include <asm/io.h>
DECLARE_GLOBAL_DATA_PTR;
int board_init(void)
{
+ bool sdmc_unlocked;
+ u32 val;
+
+ /* iLPC2AHB */
+ val = readl(AST_SCU_BASE + AST_SCU_HW_STRAP1);
+ val |= SCU_HW_STRAP_LPC_DEC_SUPER_IO;
+ writel(val, AST_SCU_BASE + AST_SCU_HW_STRAP1);
+
+ val = readl(AST_LPC_BASE + AST_LPC_HICRB);
+ val |= LPC_HICRB_ILPC2AHB;
+ writel(val, AST_LPC_BASE + AST_LPC_HICRB);
+
+ /* P2A, PCIe BMC */
+ val = readl(AST_SCU_BASE + AST_SCU_PCIE_CONFIG_SET);
+ val &= ~(SCU_PCIE_CONFIG_SET_BMC_DMA
+ | SCU_PCIE_CONFIG_SET_BMC_MMIO
+ | SCU_PCIE_CONFIG_SET_BMC_EN
+ | SCU_PCIE_CONFIG_SET_VGA_MMIO);
+ writel(val, AST_SCU_BASE + AST_SCU_PCIE_CONFIG_SET);
+
+ /* Debug UART */
+ val = readl(AST_SCU_BASE + AST_SCU_MISC1_CTRL);
+ val |= SCU_MISC_DEBUG_UART;
+ writel(val, AST_SCU_BASE + AST_SCU_MISC1_CTRL);
+
+ /* X-DMA */
+ sdmc_unlocked = readl(AST_SDMC_BASE + AST_SDMC_PROTECT);
+ if (!sdmc_unlocked)
+ writel(SDMC_PROTECT_UNLOCK, AST_SDMC_BASE + AST_SDMC_PROTECT);
+
+ val = readl(AST_SDMC_BASE + AST_SDMC_GFX_PROT);
+ val |= (SDMC_GFX_PROT_VGA_CURSOR
+ | SDMC_GFX_PROT_VGA_CG_READ
+ | SDMC_GFX_PROT_VGA_ASCII_READ
+ | SDMC_GFX_PROT_VGA_CRT
+ | SDMC_GFX_PROT_PCIE
+ | SDMC_GFX_PROT_XDMA);
+ writel(val, AST_SDMC_BASE + AST_SDMC_GFX_PROT);
+
+ if (!sdmc_unlocked)
+ writel(~SDMC_PROTECT_UNLOCK, AST_SDMC_BASE + AST_SDMC_PROTECT);
+
+ /* LPC2AHB */
+ val = readl(AST_LPC_BASE + AST_LPC_HICR5);
+ val &= ~LPC_HICR5_ENFWH;
+ writel(val, AST_LPC_BASE + AST_LPC_HICR5);
+
gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
gd->flags = 0;
--
2.19.1
meta-phosphor/dynamic-layers/aspeed-layer/recipes-bsp/u-boot/files/0001-configs-ast-Add-redundnant-env.patch
+33
View File
@@ -0,0 +1,33 @@
From 8ef2f4dcd208e072ab491874c06722c3a8ec69e3 Mon Sep 17 00:00:00 2001
From: "Edward A. James" <eajames@us.ibm.com>
Date: Thu, 13 Jul 2017 13:42:18 -0500
Subject: [PATCH 1/4] configs/ast: Add redundnant env
Configure ast chips to run redundant u-boot environments.
Signed-off-by: Edward A. James <eajames@us.ibm.com>
---
include/configs/ast-common.h | 5 ++++-
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/include/configs/ast-common.h b/include/configs/ast-common.h
index eff6d2b529..a0243083bd 100644
--- a/include/configs/ast-common.h
+++ b/include/configs/ast-common.h
@@ -104,9 +104,12 @@
#define CONFIG_SYS_MAX_FLASH_SECT (8192) /* max number of sectors on one chip */
#define CONFIG_ENV_IS_IN_FLASH 1
#define CONFIG_ENV_ADDR (AST_FMC_CS0_BASE + 0x60000)
+#define CONFIG_ENV_ADDR_REDUND (AST_FMC_CS0_BASE + 0x70000)
#define CONFIG_ENV_OFFSET 0x60000 /* environment starts here */
-#define CONFIG_ENV_SIZE 0x20000 /* Total Size of Environment Sector */
+#define CONFIG_ENV_OFFSET_REDUND 0x70000
+#define CONFIG_ENV_SIZE 0x10000 /* Total Size of Environment Sector */
+#define CONFIG_ENV_SIZE_REDUND 0x10000
#define CONFIG_BOOTCOMMAND "bootm 20080000"
#define CONFIG_ENV_OVERWRITE
--
2.14.3
meta-phosphor/dynamic-layers/aspeed-layer/recipes-bsp/u-boot/files/0002-board-aspeed-aspeednic-Use-MAC2-for-networking.patch
+43
View File
@@ -0,0 +1,43 @@
From cbb09e400a5283e5b543e2b01b8c0038890a5260 Mon Sep 17 00:00:00 2001
From: Xo Wang <xow@google.com>
Date: Thu, 20 Oct 2016 17:42:13 -0700
Subject: [PATCH 2/2] board/aspeed, aspeednic: Use MAC2 for networking
Enable and select MAC2 for aspeednic.
Signed-off-by: Xo Wang <xow@google.com>
---
drivers/net/aspeednic.c | 4 ++--
include/configs/ast-g5-ncsi.h | 1 +
2 files changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers/net/aspeednic.c b/drivers/net/aspeednic.c
index 8b85893..cff8370 100644
--- a/drivers/net/aspeednic.c
+++ b/drivers/net/aspeednic.c
@@ -18,8 +18,8 @@
/* From the board config file */
#define CONFIG_MAC1_PHY_SETTING 2
#define CONFIG_MAC2_PHY_SETTING 0
-#define CONFIG_ASPEED_MAC_NUMBER 1
-#define CONFIG_ASPEED_MAC_CONFIG 1 // config MAC1
+#define CONFIG_ASPEED_MAC_NUMBER 2
+#define CONFIG_ASPEED_MAC_CONFIG 2 // config MAC2
#define _PHY_SETTING_CONCAT(mac) CONFIG_MAC##mac##_PHY_SETTING
#define _GET_MAC_PHY_SETTING(mac) _PHY_SETTING_CONCAT(mac)
#define CONFIG_ASPEED_MAC_PHY_SETTING \
diff --git a/include/configs/ast-g5-ncsi.h b/include/configs/ast-g5-ncsi.h
index f73a8f1..1408618 100644
--- a/include/configs/ast-g5-ncsi.h
+++ b/include/configs/ast-g5-ncsi.h
@@ -22,6 +22,7 @@
/* Ethernet */
#define CONFIG_LIB_RAND
#define CONFIG_ASPEEDNIC
+#define CONFIG_MAC2_ENABLE
/* platform.S settings */
#define CONFIG_DRAM_ECC_SIZE 0x10000000
--
2.8.0.rc3.226.g39d4020
meta-phosphor/dynamic-layers/aspeed-layer/recipes-bsp/u-boot/files/0002-config-ast-common-hack-bootopts.patch
+28
View File
@@ -0,0 +1,28 @@
From c678bbdad037604850613e775baacc52ed92c9c1 Mon Sep 17 00:00:00 2001
From: Patrick Williams <patrick@stwcx.xyz>
Date: Fri, 21 Jul 2017 16:30:01 -0500
Subject: [PATCH 2/4] config/ast-common: hack bootopts
Signed-off-by: Patrick Williams <patrick@stwcx.xyz>
---
include/configs/ast-common.h | 3 +++
1 file changed, 3 insertions(+)
diff --git a/include/configs/ast-common.h b/include/configs/ast-common.h
index a0243083bd..7ddba62298 100644
--- a/include/configs/ast-common.h
+++ b/include/configs/ast-common.h
@@ -96,7 +96,10 @@
#define CONFIG_CMD_MTDPARTS
#endif
+#if 0
#define CONFIG_BOOTARGS "console=ttyS4,115200n8 root=/dev/ram rw"
+#endif
+#define CONFIG_BOOTARGS "console=ttyS4,115200n8 root=/dev/mtdblock4 ro"
#define CONFIG_AST_SPI_NOR /* AST SPI NOR Flash */
#define CONFIG_FMC_CS 1
--
2.14.3
meta-phosphor/dynamic-layers/aspeed-layer/recipes-bsp/u-boot/files/0003-config-ast-common-Add-bootopts-to-support-ubi-and-mt.patch
+69
View File
@@ -0,0 +1,69 @@
From 0c77be343fc4781719dcc0748bc29a26ea83e0a3 Mon Sep 17 00:00:00 2001
From: Adriana Kobylak <anoo@us.ibm.com>
Date: Wed, 9 Aug 2017 14:11:56 -0500
Subject: [PATCH 3/4] config/ast-common: Add bootopts to support ubi and mtd
partitioning
Signed-off-by: Adriana Kobylak <anoo@us.ibm.com>
---
include/configs/ast-common.h | 19 +++++++++++++++++--
1 file changed, 17 insertions(+), 2 deletions(-)
diff --git a/include/configs/ast-common.h b/include/configs/ast-common.h
index 7ddba62298..14191e4ab0 100644
--- a/include/configs/ast-common.h
+++ b/include/configs/ast-common.h
@@ -84,6 +84,12 @@
#define CONFIG_SYS_MAXARGS 16
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
+/*
+ * Dynamic MTD Partition support
+ */
+#define MTDIDS_DEFAULT "nor0=bmc"
+#define MTDPARTS_DEFAULT "mtdparts=bmc:384k(u-boot),128k(u-boot-env),-(obmc-ubi)"
+
/*
* Optional MTD and UBI support
*/
@@ -99,7 +105,7 @@
#if 0
#define CONFIG_BOOTARGS "console=ttyS4,115200n8 root=/dev/ram rw"
#endif
-#define CONFIG_BOOTARGS "console=ttyS4,115200n8 root=/dev/mtdblock4 ro"
+#define CONFIG_BOOTARGS "console=ttyS4,115200n8 ubi.mtd=obmc-ubi,0,0,0 ubi.mtd=alt-obmc-ubi,0,0,4 ro rootfstype=squashfs"
#define CONFIG_AST_SPI_NOR /* AST SPI NOR Flash */
#define CONFIG_FMC_CS 1
@@ -108,18 +114,27 @@
#define CONFIG_ENV_IS_IN_FLASH 1
#define CONFIG_ENV_ADDR (AST_FMC_CS0_BASE + 0x60000)
#define CONFIG_ENV_ADDR_REDUND (AST_FMC_CS0_BASE + 0x70000)
+#define CONFIG_LOADADDR 80800000
#define CONFIG_ENV_OFFSET 0x60000 /* environment starts here */
#define CONFIG_ENV_OFFSET_REDUND 0x70000
#define CONFIG_ENV_SIZE 0x10000 /* Total Size of Environment Sector */
#define CONFIG_ENV_SIZE_REDUND 0x10000
-#define CONFIG_BOOTCOMMAND "bootm 20080000"
+#define CONFIG_BOOTCOMMAND "run set_bootargs; run obmc_bootcmd"
#define CONFIG_ENV_OVERWRITE
#define ASPEED_ENV_SETTINGS \
+ "ubiblock=0,1 \0" \
+ "root=/dev/ubiblock0_1 \0" \
+ "kernelname=kernel-0 \0" \
+ "loadaddr=" __stringify(CONFIG_LOADADDR) "\0" \
+ "set_bootargs=setenv bootargs " CONFIG_BOOTARGS " ubi.block=\${ubiblock} root=\${root} \0" \
+ "obmc_bootcmd=ubi part obmc-ubi; ubi read ${loadaddr} ${kernelname}; bootm ${loadaddr} \0" \
"verify=yes\0" \
"spi_dma=yes\0" \
+ "mtdids=" MTDIDS_DEFAULT "\0" \
+ "mtdparts=" MTDPARTS_DEFAULT "\0" \
""
#endif /* __AST_COMMON_CONFIG_H */
--
2.14.3
meta-phosphor/dynamic-layers/aspeed-layer/recipes-bsp/u-boot/files/0004-config-ast-common-Add-conditional-factory-reset-comm.patch
+46
View File
@@ -0,0 +1,46 @@
From 878651bbaa8a7da203fafccb164ca7b32287b8f9 Mon Sep 17 00:00:00 2001
From: "Edward A. James" <eajames@us.ibm.com>
Date: Thu, 9 Nov 2017 11:39:10 -0600
Subject: [PATCH 4/4] config/ast-common: Add conditional factory reset command
Factory reset (removing persistent rwfs) has to occur before we've
mounted the rwfs. However, the variable to determine whether or not to
do the reset is stored in the u-boot env. This is tricky to access
before rwfs is mounted except in u-boot. So, check it before every boot.
Signed-off-by: Edward A. James <eajames@us.ibm.com>
---
include/configs/ast-common.h | 6 +++++-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/include/configs/ast-common.h b/include/configs/ast-common.h
index 14191e4ab0..aaa5155e00 100644
--- a/include/configs/ast-common.h
+++ b/include/configs/ast-common.h
@@ -121,6 +121,8 @@
#define CONFIG_ENV_SIZE 0x10000 /* Total Size of Environment Sector */
#define CONFIG_ENV_SIZE_REDUND 0x10000
+#define CONFIG_RWFS_SIZE 0x600000
+
#define CONFIG_BOOTCOMMAND "run set_bootargs; run obmc_bootcmd"
#define CONFIG_ENV_OVERWRITE
@@ -130,11 +132,13 @@
"kernelname=kernel-0 \0" \
"loadaddr=" __stringify(CONFIG_LOADADDR) "\0" \
"set_bootargs=setenv bootargs " CONFIG_BOOTARGS " ubi.block=\${ubiblock} root=\${root} \0" \
- "obmc_bootcmd=ubi part obmc-ubi; ubi read ${loadaddr} ${kernelname}; bootm ${loadaddr} \0" \
+ "obmc_bootcmd=ubi part obmc-ubi; run do_rwreset; ubi read ${loadaddr} ${kernelname}; bootm ${loadaddr} \0" \
"verify=yes\0" \
"spi_dma=yes\0" \
"mtdids=" MTDIDS_DEFAULT "\0" \
"mtdparts=" MTDPARTS_DEFAULT "\0" \
+ "rwfs_size=" __stringify(CONFIG_RWFS_SIZE) "\0" \
+ "do_rwreset=if test \"\${rwreset}\" = \"true\"; then ubi remove rwfs; ubi create rwfs \${rwfs_size}; fi \0" \
""
#endif /* __AST_COMMON_CONFIG_H */
--
2.14.3
meta-phosphor/dynamic-layers/aspeed-layer/recipes-bsp/u-boot/files/0005-config-ast-common-Fall-back-to-secondary-flash-on-fa.patch
+34
View File
@@ -0,0 +1,34 @@
From 345b1ade63576f5a8a1c3a4a1b75aab41d84b714 Mon Sep 17 00:00:00 2001
From: Andrew Jeffery <andrew@aj.id.au>
Date: Fri, 20 Apr 2018 13:29:58 +0930
Subject: [PATCH] config/ast-common: Fall-back to secondary flash on failed
bootm
Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
---
include/configs/ast-common.h | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/include/configs/ast-common.h b/include/configs/ast-common.h
index ad08016ec110..10ef6a1955b7 100644
--- a/include/configs/ast-common.h
+++ b/include/configs/ast-common.h
@@ -127,12 +127,14 @@
#define CONFIG_ENV_OVERWRITE
#define ASPEED_ENV_SETTINGS \
+ "wdt2bite=mw.l 0x1e785024 0xa 1; mw.b 0x1e78502c 0xb3 1 \0" \
+ "bootalt=run wdt2bite \0" \
"ubiblock=0,1 \0" \
"root=/dev/ubiblock0_1 \0" \
"kernelname=kernel-0 \0" \
"loadaddr=" __stringify(CONFIG_LOADADDR) "\0" \
"set_bootargs=setenv bootargs " CONFIG_BOOTARGS " ubi.block=\${ubiblock} root=\${root} \0" \
- "obmc_bootcmd=ubi part obmc-ubi; run do_rwreset; ubi read ${loadaddr} ${kernelname}; bootm ${loadaddr} \0" \
+ "obmc_bootcmd=ubi part obmc-ubi; run do_rwreset; ubi read ${loadaddr} ${kernelname}; bootm ${loadaddr} || run bootalt \0" \
"verify=yes\0" \
"spi_dma=yes\0" \
"mtdids=" MTDIDS_DEFAULT "\0" \
--
2.14.1
meta-phosphor/dynamic-layers/aspeed-layer/recipes-bsp/u-boot/files/0006-aspeed-Enable-SPI-master-mode-by-default.patch
+34
View File
@@ -0,0 +1,34 @@
From 7947dbbfb21e10e8fb0f852a14485cedf5df1d36 Mon Sep 17 00:00:00 2001
From: Chanh Nguyen <chanh@os.amperecomputing.com>
Date: Sun, 10 Oct 2021 11:57:20 +0700
Subject: [PATCH] aspeed: Enable SPI master mode by default
The ast2500 share the RGMII1 pin and the hw strap pins
for SPI interface mode selection ( pin[12:13] ).
In some systems, the RGMII/NCSI interface will use the pin.
It makes the SPI interface mode setting is not correct.
This patch will enable the SPI master mode by default.
Signed-off-by: Chanh Nguyen <chanh@os.amperecomputing.com>
---
board/aspeed/ast-g5/ast-g5.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/board/aspeed/ast-g5/ast-g5.c b/board/aspeed/ast-g5/ast-g5.c
index e67a4bf8b2..82e9f81acc 100644
--- a/board/aspeed/ast-g5/ast-g5.c
+++ b/board/aspeed/ast-g5/ast-g5.c
@@ -21,6 +21,9 @@ int board_init(void)
gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
gd->flags = 0;
+ //pin switch by trap[13:12] -- [0:1] Enable SPI Master
+ ast_scu_spi_master(1); /* enable SPI master */
+
return 0;
}
--
2.17.1
meta-phosphor/dynamic-layers/aspeed-layer/recipes-bsp/u-boot/u-boot-aspeed-sdk_%.bbappend
+1
View File
@@ -0,0 +1 @@
ASPEED_IMAGE_SIZE_KB = "${FLASH_SIZE}"
meta-phosphor/dynamic-layers/aspeed-layer/recipes-bsp/u-boot/u-boot-aspeed.inc
+32
View File
@@ -0,0 +1,32 @@
inherit image_version
SRC_URI:append:aspeed = " file://0001-configs-ast-Add-redundnant-env.patch"
SRC_URI:append:aspeed:df-obmc-ubi-fs = " \
file://0002-config-ast-common-hack-bootopts.patch \
file://0003-config-ast-common-Add-bootopts-to-support-ubi-and-mt.patch \
file://0004-config-ast-common-Add-conditional-factory-reset-comm.patch \
file://0005-config-ast-common-Fall-back-to-secondary-flash-on-fa.patch \
"
SRC_URI:append:aspeed:df-isolate-bmc = " \
file://0001-aspeed-Disable-unnecessary-features.patch \
"
SRC_URI:append:aspeed:df-aspeednic-use-mac2 = " \
file://0002-board-aspeed-aspeednic-Use-MAC2-for-networking.patch \
"
SRC_URI:append:aspeed:df-aspeed-spi-master = " \
file://0006-aspeed-Enable-SPI-master-mode-by-default.patch \
"
do_patch[depends] += "os-release:do_populate_sysroot"
python do_patch:append:aspeed:df-obmc-ubi-fs () {
version_id=do_get_versionID(d)
d.setVar('VERSION_ID', version_id)
bb.build.exec_func("patch_kernelname", d)
}
patch_kernelname () {
sed -ri "s/kernel-(0|[a-fA-F0-9]{8})/kernel-${VERSION_ID}/g" \
${S}/include/configs/ast-common.h &> /dev/null
}
meta-phosphor/dynamic-layers/aspeed-layer/recipes-bsp/u-boot/u-boot-aspeed_%.bbappend
+4
View File
@@ -0,0 +1,4 @@
FILESEXTRAPATHS:prepend := "${THISDIR}/files:"
require u-boot-aspeed.inc
require recipes-bsp/u-boot/u-boot-obmc.inc
meta-phosphor/dynamic-layers/aspeed-layer/recipes-bsp/u-boot/u-boot-fw-utils-aspeed_%.bbappend
+3
View File
@@ -0,0 +1,3 @@
FILESEXTRAPATHS:prepend := "${THISDIR}/files:"
require u-boot-aspeed.inc
meta-phosphor/dynamic-layers/aspeed-layer/recipes-kernel/cf-fsi-firmware/cf-fsi-firmware_git.bb
+28
View File
@@ -0,0 +1,28 @@
SUMMARY = "Firmware for using the ASPEED ColdFire FSI master"
SECTION = "kernel"
LICENSE = "GPL-2.0-or-later"
LIC_FILES_CHKSUM = "file://COPYING;md5=d7810fab7487fb0aad327b76f1be7cd7"
SRCREV = "bae32e353a3641b5164211f6bf06c5620f6e384d"
SRC_URI = "git://github.com/ozbenh/cf-fsi.git;branch=master;protocol=https"
PR = "r1"
PV = "1.0+git${SRCPV}"
S = "${WORKDIR}/git"
inherit allarch
do_compile() {
:
}
firmware_dir="${nonarch_base_libdir}/firmware/"
do_install() {
install -d ${D}${firmware_dir}
install -m 0644 ${S}/dist-bin/cf-fsi-fw.bin ${D}${firmware_dir}
}
FILES:${PN} = "${firmware_dir}"
meta-phosphor/dynamic-layers/nuvoton-layer/recipes-bsp/u-boot/u-boot-nuvoton_%.bbappend
+1
View File
@@ -0,0 +1 @@
require recipes-bsp/u-boot/u-boot-obmc.inc
meta-phosphor/dynamic-layers/nuvoton-layer/recipes-kernel/linux/linux-nuvoton_%.bbappend
+5
View File
@@ -0,0 +1,5 @@
FILESEXTRAPATHS:prepend := "${THISDIR}/${PN}:"
# OpenBMC loads in kernel features via other mechanisms so this check
# in the kernel-yocto.bbclass is not required
KERNEL_DANGLING_FEATURES_WARN_ONLY = "1"
meta-phosphor/dynamic-layers/nuvoton-layer/recipes-phosphor/host/phosphor-host-postd_%.bbappend
+1
View File
@@ -0,0 +1 @@
SNOOP_DEVICE:npcm7xx = "npcm7xx-lpc-bpc0"
meta-phosphor/dynamic-layers/tpm-layer/recipes-core/packagegroups/packagegroup-security-tpm2.bbappend
+3
View File
@@ -0,0 +1,3 @@
# We don't need pkcs11 support on the BMC by default and it ends up causing a
# dependency chain that brings in Rust.
RDEPENDS:packagegroup-security-tpm2:remove = "tpm2-pkcs11"