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2026-04-23 17:07:55 +08:00
commit b7e39e063b
16725 changed files with 1625565 additions and 0 deletions
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meta-luxshare/meta-bhs/recipes-kernel/linux/linux-aspeed/0001-Add-Aspeed-JTAG-Driver-Into-Linux-Kernel.patch
Executable
+2570
View File
File diff suppressed because it is too large Load Diff
meta-luxshare/meta-bhs/recipes-kernel/linux/linux-aspeed/0001-Add-WA-to-enable-i3c1-as-i3c1-PVNN_MAIN_CPU1-voltage.patch
Executable
+155
View File
@@ -0,0 +1,155 @@
From 1d2fac5f2cd1f44a5e93151fe2e6e6ddb43bf126 Mon Sep 17 00:00:00 2001
From: wangjue <jue.wang2@luxshare-ict.com>
Date: Wed, 27 Nov 2024 12:25:57 +0800
Subject: [PATCH] Add WA to enable i3c1 as i3c1 PVNN_MAIN_CPU1 voltage not
available when bmc kernel bootup
Signed-off-by: wangjue <jue.wang2@luxshare-ict.com>
---
drivers/i3c/master.c | 11 +++--
drivers/i3c/master/dw-i3c-master.c | 79 ++++++++++++++++++++++++++++--
2 files changed, 83 insertions(+), 7 deletions(-)
diff --git a/drivers/i3c/master.c b/drivers/i3c/master.c
index 534db4f05deb..3f210541cb49 100644
--- a/drivers/i3c/master.c
+++ b/drivers/i3c/master.c
@@ -2072,9 +2072,12 @@ static int i3c_master_bus_init(struct i3c_master_controller *master)
* Reset all dynamic address that may have been assigned before
* (assigned by the bootloader for example).
*/
- ret = i3c_master_rstdaa_locked(master, I3C_BROADCAST_ADDR);
- if (ret && ret != I3C_ERROR_M2)
- goto err_bus_cleanup;
+ if (!master->jdec_spd) {
+ ret = i3c_master_rstdaa_locked(master, I3C_BROADCAST_ADDR);
+ if (ret && ret != I3C_ERROR_M2)
+ goto err_bus_cleanup;
+ }
+
/*
* Reserve init_dyn_addr first, and then try to pre-assign dynamic
@@ -2121,7 +2124,7 @@ static int i3c_master_bus_init(struct i3c_master_controller *master)
* Since SPD devices are all with static address. Don't do DAA if we
* know it is a pure I2C bus.
*/
- if (master->jdec_spd && n_i3cdev == 0)
+ if (master->jdec_spd)
return 0;
ret = i3c_master_do_daa(master);
diff --git a/drivers/i3c/master/dw-i3c-master.c b/drivers/i3c/master/dw-i3c-master.c
index 6d1ba40eca0f..1ad8a0bba7dc 100644
--- a/drivers/i3c/master/dw-i3c-master.c
+++ b/drivers/i3c/master/dw-i3c-master.c
@@ -374,8 +374,16 @@
#define AST2600_I3C_IBI_MAX_PAYLOAD 255
-#define SEL_CPU0_I3C_DDR_GPIO 921
-#define SEL_CPU1_I3C_DDR_GPIO 922
+#define SEL_CPU0_I3C_DDR_GPIO 921
+#define SEL_CPU1_I3C_DDR_GPIO 922
+#define I3C_SPD_BMC_MUX0_SEL 1004
+#define I3C_SPD_BMC_MUX0_EN 852
+#define I3C_SPD_BMC_MUX1_SEL 1005
+#define I3C_SPD_BMC_MUX1_EN 853
+#define I3C_SPD_BMC_MUX2_SEL 1006
+#define I3C_SPD_BMC_MUX2_EN 854
+#define I3C_SPD_BMC_MUX3_SEL 1007
+#define I3C_SPD_BMC_MUX3_EN 909
struct dw_i3c_master_caps {
u8 cmdfifodepth;
@@ -3141,6 +3149,69 @@ static void i3c_gpio_switch_bios(struct dw_i3c_master *master)
gpio_free(SEL_CPU1_I3C_DDR_GPIO);
}
+static void i3c_gpio_switch_dimm(struct dw_i3c_master *master)
+{
+ if (gpio_request(I3C_SPD_BMC_MUX0_SEL, "dw-i3c-master")) {
+ dev_err(master->dev, "unable to allocate I3C_SPD_BMC_MUX0_SEL\n");
+ return;
+ }
+
+ if (gpio_request(I3C_SPD_BMC_MUX0_EN, "dw-i3c-master")) {
+ dev_err(master->dev, "unable to allocate I3C_SPD_BMC_MUX0_EN\n");
+ return;
+ }
+
+ if (gpio_request(I3C_SPD_BMC_MUX1_SEL, "dw-i3c-master")) {
+ dev_err(master->dev, "unable to allocate I3C_SPD_BMC_MUX1_SEL\n");
+ return;
+ }
+
+ if (gpio_request(I3C_SPD_BMC_MUX1_EN, "dw-i3c-master")) {
+ dev_err(master->dev, "unable to allocate I3C_SPD_BMC_MUX1_EN\n");
+ return;
+ }
+
+ if (gpio_request(I3C_SPD_BMC_MUX2_SEL, "dw-i3c-master")) {
+ dev_err(master->dev, "unable to allocate I3C_SPD_BMC_MUX2_SEL\n");
+ return;
+ }
+
+ if (gpio_request(I3C_SPD_BMC_MUX2_EN, "dw-i3c-master")) {
+ dev_err(master->dev, "unable to allocate I3C_SPD_BMC_MUX2_EN\n");
+ return;
+ }
+
+ if (gpio_request(I3C_SPD_BMC_MUX3_SEL, "dw-i3c-master")) {
+ dev_err(master->dev, "unable to allocate I3C_SPD_BMC_MUX3_SEL\n");
+ return;
+ }
+
+ if (gpio_request(I3C_SPD_BMC_MUX3_EN, "dw-i3c-master")) {
+ dev_err(master->dev, "unable to allocate I3C_SPD_BMC_MUX3_EN\n");
+ return;
+ }
+
+ gpio_direction_output(I3C_SPD_BMC_MUX0_SEL, 0);
+ gpio_direction_output(I3C_SPD_BMC_MUX0_EN, 0);
+ gpio_direction_output(I3C_SPD_BMC_MUX1_SEL, 1);
+ gpio_direction_output(I3C_SPD_BMC_MUX1_EN, 1);
+ gpio_direction_output(I3C_SPD_BMC_MUX2_SEL, 0);
+ gpio_direction_output(I3C_SPD_BMC_MUX2_EN, 0);
+ gpio_direction_output(I3C_SPD_BMC_MUX3_SEL, 1);
+ gpio_direction_output(I3C_SPD_BMC_MUX3_EN, 1);
+
+ usleep_range(500, 1000);
+
+ gpio_free(I3C_SPD_BMC_MUX0_SEL);
+ gpio_free(I3C_SPD_BMC_MUX0_EN);
+ gpio_free(I3C_SPD_BMC_MUX1_SEL);
+ gpio_free(I3C_SPD_BMC_MUX1_EN);
+ gpio_free(I3C_SPD_BMC_MUX2_SEL);
+ gpio_free(I3C_SPD_BMC_MUX2_EN);
+ gpio_free(I3C_SPD_BMC_MUX3_SEL);
+ gpio_free(I3C_SPD_BMC_MUX3_EN);
+}
+
static int dw_i3c_probe(struct platform_device *pdev)
{
const struct of_device_id *match;
@@ -3155,6 +3226,9 @@ static int dw_i3c_probe(struct platform_device *pdev)
master->dev = &pdev->dev;
master->base.bus_driver_context = master;
+ i3c_gpio_switch_bmc(master);
+ i3c_gpio_switch_dimm(master);
+
master->regs = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(master->regs))
return PTR_ERR(master->regs);
@@ -3180,7 +3254,6 @@ static int dw_i3c_probe(struct platform_device *pdev)
spin_lock_init(&master->ibi.master.lock);
platform_set_drvdata(pdev, master);
- i3c_gpio_switch_bmc(master);
/* Information regarding the FIFOs/QUEUEs depth */
ret = readl(master->regs + QUEUE_STATUS_LEVEL);
--
2.34.1
meta-luxshare/meta-bhs/recipes-kernel/linux/linux-aspeed/0001-Add-sw-workaround-to-let-all-dimm-spd-devices-to-rec.patch
Executable
+399
View File
@@ -0,0 +1,399 @@
From 136ea6342d8de89ab6166dfce0ba20f67aabc0d3 Mon Sep 17 00:00:00 2001
From: wangjue <jue.wang2@luxshare-ict.com>
Date: Thu, 9 Oct 2025 10:49:32 +0800
Subject: [PATCH] Add sw workaround to let all dimm spd devices to receive ccc
message
Signed-off-by: wangjue <jue.wang2@luxshare-ict.com>
---
drivers/i3c/master.c | 251 ++++++++++++++++++++++++++++++-------
include/linux/i3c/master.h | 11 ++
2 files changed, 214 insertions(+), 48 deletions(-)
diff --git a/drivers/i3c/master.c b/drivers/i3c/master.c
index 534db4f05deb..9cd566d3928f 100644
--- a/drivers/i3c/master.c
+++ b/drivers/i3c/master.c
@@ -16,12 +16,117 @@
#include <linux/slab.h>
#include <linux/spinlock.h>
#include <linux/workqueue.h>
+#include <linux/gpio.h>
+#include <linux/delay.h>
#include "internals.h"
static DEFINE_IDR(i3c_bus_idr);
static DEFINE_MUTEX(i3c_core_lock);
+static void i3c_gpio_switch_init(struct i3c_master_controller *master)
+{
+ if (gpio_request(I3C_SPD_BMC_MUX0_SEL, "dw-i3c-master")) {
+ dev_err(&master->dev, "unable to allocate I3C_SPD_BMC_MUX0_SEL\n");
+ return;
+ }
+
+ if (gpio_request(I3C_SPD_BMC_MUX0_EN, "dw-i3c-master")) {
+ dev_err(&master->dev, "unable to allocate I3C_SPD_BMC_MUX0_EN\n");
+ return;
+ }
+
+ if (gpio_request(I3C_SPD_BMC_MUX1_SEL, "dw-i3c-master")) {
+ dev_err(&master->dev, "unable to allocate I3C_SPD_BMC_MUX1_SEL\n");
+ return;
+ }
+
+ if (gpio_request(I3C_SPD_BMC_MUX1_EN, "dw-i3c-master")) {
+ dev_err(&master->dev, "unable to allocate I3C_SPD_BMC_MUX1_EN\n");
+ return;
+ }
+
+ if (gpio_request(I3C_SPD_BMC_MUX2_SEL, "dw-i3c-master")) {
+ dev_err(&master->dev, "unable to allocate I3C_SPD_BMC_MUX2_SEL\n");
+ return;
+ }
+
+ if (gpio_request(I3C_SPD_BMC_MUX2_EN, "dw-i3c-master")) {
+ dev_err(&master->dev, "unable to allocate I3C_SPD_BMC_MUX2_EN\n");
+ return;
+ }
+
+ if (gpio_request(I3C_SPD_BMC_MUX3_SEL, "dw-i3c-master")) {
+ dev_err(&master->dev, "unable to allocate I3C_SPD_BMC_MUX3_SEL\n");
+ return;
+ }
+
+ if (gpio_request(I3C_SPD_BMC_MUX3_EN, "dw-i3c-master")) {
+ dev_err(&master->dev, "unable to allocate I3C_SPD_BMC_MUX3_EN\n");
+ return;
+ }
+}
+
+static void i3c_gpio_switch_free(void)
+{
+ gpio_free(I3C_SPD_BMC_MUX0_SEL);
+ gpio_free(I3C_SPD_BMC_MUX0_EN);
+ gpio_free(I3C_SPD_BMC_MUX1_SEL);
+ gpio_free(I3C_SPD_BMC_MUX1_EN);
+ gpio_free(I3C_SPD_BMC_MUX2_SEL);
+ gpio_free(I3C_SPD_BMC_MUX2_EN);
+ gpio_free(I3C_SPD_BMC_MUX3_SEL);
+ gpio_free(I3C_SPD_BMC_MUX3_EN);
+}
+
+static void i3c_gpio_switch_dimm_group(int gNum)
+{
+ if(gNum == 0)
+ {
+ gpio_direction_output(I3C_SPD_BMC_MUX0_SEL, 0);
+ gpio_direction_output(I3C_SPD_BMC_MUX0_EN, 0);
+ gpio_direction_output(I3C_SPD_BMC_MUX1_SEL, 1);
+ gpio_direction_output(I3C_SPD_BMC_MUX1_EN, 1);
+ gpio_direction_output(I3C_SPD_BMC_MUX2_SEL, 0);
+ gpio_direction_output(I3C_SPD_BMC_MUX2_EN, 0);
+ gpio_direction_output(I3C_SPD_BMC_MUX3_SEL, 1);
+ gpio_direction_output(I3C_SPD_BMC_MUX3_EN, 1);
+ }
+ if(gNum == 1)
+ {
+ gpio_direction_output(I3C_SPD_BMC_MUX0_SEL, 1);
+ gpio_direction_output(I3C_SPD_BMC_MUX0_EN, 0);
+ gpio_direction_output(I3C_SPD_BMC_MUX1_SEL, 1);
+ gpio_direction_output(I3C_SPD_BMC_MUX1_EN, 1);
+ gpio_direction_output(I3C_SPD_BMC_MUX2_SEL, 1);
+ gpio_direction_output(I3C_SPD_BMC_MUX2_EN, 0);
+ gpio_direction_output(I3C_SPD_BMC_MUX3_SEL, 1);
+ gpio_direction_output(I3C_SPD_BMC_MUX3_EN, 1);
+ }
+ if(gNum == 2)
+ {
+ gpio_direction_output(I3C_SPD_BMC_MUX0_SEL, 1);
+ gpio_direction_output(I3C_SPD_BMC_MUX0_EN, 1);
+ gpio_direction_output(I3C_SPD_BMC_MUX1_SEL, 0);
+ gpio_direction_output(I3C_SPD_BMC_MUX1_EN, 0);
+ gpio_direction_output(I3C_SPD_BMC_MUX2_SEL, 1);
+ gpio_direction_output(I3C_SPD_BMC_MUX2_EN, 1);
+ gpio_direction_output(I3C_SPD_BMC_MUX3_SEL, 0);
+ gpio_direction_output(I3C_SPD_BMC_MUX3_EN, 0);
+ }
+ if(gNum == 3)
+ {
+ gpio_direction_output(I3C_SPD_BMC_MUX0_SEL, 1);
+ gpio_direction_output(I3C_SPD_BMC_MUX0_EN, 1);
+ gpio_direction_output(I3C_SPD_BMC_MUX1_SEL, 1);
+ gpio_direction_output(I3C_SPD_BMC_MUX1_EN, 0);
+ gpio_direction_output(I3C_SPD_BMC_MUX2_SEL, 1);
+ gpio_direction_output(I3C_SPD_BMC_MUX2_EN, 1);
+ gpio_direction_output(I3C_SPD_BMC_MUX3_SEL, 1);
+ gpio_direction_output(I3C_SPD_BMC_MUX3_EN, 0);
+ }
+}
+
/**
* i3c_bus_maintenance_lock - Lock the bus for a maintenance operation
* @bus: I3C bus to take the lock on
@@ -593,39 +698,51 @@ static ssize_t rescan_store(struct device *dev, struct device_attribute *attr,
if (!res)
return count;
+ i3c_gpio_switch_init(master);
+
i3c_device_publish_event(master, i3c_event_prepare_for_rescan);
- i3c_bus_maintenance_lock(bus);
+ for(int i=0; i<4; i++) {
+ i3c_gpio_switch_dimm_group(i);
+ usleep_range(2000, 2100);
- ret = i3c_master_disec_locked(master, I3C_BROADCAST_ADDR,
- I3C_CCC_EVENT_SIR | I3C_CCC_EVENT_MR |
- I3C_CCC_EVENT_HJ);
- if (ret && ret != I3C_ERROR_M2) {
- dev_dbg(&master->dev,
- "Failed to run broadcast DISEC for rescan, ret=%d\n", ret);
- i3c_bus_maintenance_unlock(bus);
- return ret;
- }
+ i3c_bus_maintenance_lock(bus);
+
+ ret = i3c_master_disec_locked(master, I3C_BROADCAST_ADDR,
+ I3C_CCC_EVENT_SIR | I3C_CCC_EVENT_MR |
+ I3C_CCC_EVENT_HJ);
+ if (ret && ret != I3C_ERROR_M2) {
+ dev_dbg(&master->dev,
+ "Failed to run broadcast DISEC for rescan, ret=%d\n", ret);
+ i3c_bus_maintenance_unlock(bus);
+ i3c_gpio_switch_free();
+ return ret;
+ }
+
+ ret = i3c_master_rstdaa_locked(master, I3C_BROADCAST_ADDR);
+ if (ret && ret != I3C_ERROR_M2) {
+ dev_dbg(&master->dev,
+ "Failed to run RSTDAA for rescan, ret=%d\n", ret);
+ i3c_bus_maintenance_unlock(bus);
+ i3c_gpio_switch_free();
+ return ret;
+ }
- ret = i3c_master_rstdaa_locked(master, I3C_BROADCAST_ADDR);
- if (ret && ret != I3C_ERROR_M2) {
- dev_dbg(&master->dev,
- "Failed to run RSTDAA for rescan, ret=%d\n", ret);
i3c_bus_maintenance_unlock(bus);
- return ret;
+ usleep_range(2000, 2100);
}
- i3c_bus_maintenance_unlock(bus);
-
ret = i3c_master_do_daa(master);
if (ret) {
dev_dbg(&master->dev, "Failed to run DAA for rescan, ret=%d\n",
ret);
+ i3c_gpio_switch_free();
return ret;
}
i3c_device_publish_event(master, i3c_event_rescan_done);
+ i3c_gpio_switch_free();
return count;
}
static DEVICE_ATTR_WO(rescan);
@@ -1863,11 +1980,17 @@ int i3c_master_do_daa(struct i3c_master_controller *master)
{
int ret = 0;
+ i3c_gpio_switch_init(master);
mutex_lock(&master->daa_lock);
i3c_bus_maintenance_lock(&master->bus);
if (master->jdec_spd) {
- ret = i3c_master_sethid_locked(master);
- ret = i3c_master_setaasa_locked(master);
+ for(int i=0; i<4; i++) {
+ i3c_gpio_switch_dimm_group(i);
+ usleep_range(2000, 2100);
+ ret = i3c_master_sethid_locked(master);
+ ret = i3c_master_setaasa_locked(master);
+ usleep_range(2000, 2100);
+ }
} else {
ret = master->ops->do_daa(master);
}
@@ -1880,6 +2003,7 @@ int i3c_master_do_daa(struct i3c_master_controller *master)
mutex_unlock:
mutex_unlock(&master->daa_lock);
+ i3c_gpio_switch_free();
return ret;
}
EXPORT_SYMBOL_GPL(i3c_master_do_daa);
@@ -2011,6 +2135,7 @@ static int i3c_master_bus_init(struct i3c_master_controller *master)
struct i2c_dev_desc *i2cdev;
int ret, n_i3cdev = 0;
+ i3c_gpio_switch_init(master);
/*
* First attach all devices with static definitions provided by the
* FW.
@@ -2061,21 +2186,31 @@ static int i3c_master_bus_init(struct i3c_master_controller *master)
goto err_bus_cleanup;
}
- /* Disable all slave events before starting DAA. */
- ret = i3c_master_disec_locked(master, I3C_BROADCAST_ADDR,
- I3C_CCC_EVENT_SIR | I3C_CCC_EVENT_MR |
- I3C_CCC_EVENT_HJ);
- if (ret && ret != I3C_ERROR_M2)
- goto err_bus_cleanup;
+ for(int i=0; i<4; i++) {
+ i3c_gpio_switch_dimm_group(i);
+ usleep_range(2000, 2100);
+ /* Disable all slave events before starting DAA. */
+ ret = i3c_master_disec_locked(master, I3C_BROADCAST_ADDR,
+ I3C_CCC_EVENT_SIR | I3C_CCC_EVENT_MR |
+ I3C_CCC_EVENT_HJ);
+ if (ret && ret != I3C_ERROR_M2)
+ goto err_bus_cleanup;
+ usleep_range(2000, 2100);
+ }
- /*
- * Reset all dynamic address that may have been assigned before
- * (assigned by the bootloader for example).
- */
- ret = i3c_master_rstdaa_locked(master, I3C_BROADCAST_ADDR);
- if (ret && ret != I3C_ERROR_M2)
- goto err_bus_cleanup;
+ for(int i=0; i<4; i++) {
+ i3c_gpio_switch_dimm_group(i);
+ usleep_range(2000, 2100);
+ /*
+ * Reset all dynamic address that may have been assigned before
+ * (assigned by the bootloader for example).
+ */
+ ret = i3c_master_rstdaa_locked(master, I3C_BROADCAST_ADDR);
+ if (ret && ret != I3C_ERROR_M2)
+ goto err_bus_cleanup;
+ usleep_range(2000, 2100);
+ }
/*
* Reserve init_dyn_addr first, and then try to pre-assign dynamic
* address and retrieve device information if needed.
@@ -2117,12 +2252,16 @@ static int i3c_master_bus_init(struct i3c_master_controller *master)
n_i3cdev++;
}
+ i3c_gpio_switch_free();
+
/*
* Since SPD devices are all with static address. Don't do DAA if we
* know it is a pure I2C bus.
*/
if (master->jdec_spd && n_i3cdev == 0)
+ {
return 0;
+ }
ret = i3c_master_do_daa(master);
if (ret)
@@ -2131,7 +2270,12 @@ static int i3c_master_bus_init(struct i3c_master_controller *master)
return 0;
err_rstdaa:
- i3c_master_rstdaa_locked(master, I3C_BROADCAST_ADDR);
+ for(int i=0; i<4; i++) {
+ i3c_gpio_switch_dimm_group(i);
+ usleep_range(2000, 2100);
+ i3c_master_rstdaa_locked(master, I3C_BROADCAST_ADDR);
+ usleep_range(2000, 2100);
+ }
err_bus_cleanup:
if (master->ops->bus_cleanup)
@@ -2140,6 +2284,7 @@ static int i3c_master_bus_init(struct i3c_master_controller *master)
err_detach_devs:
i3c_master_detach_free_devs(master);
+ i3c_gpio_switch_free();
return ret;
}
@@ -2147,27 +2292,37 @@ static void i3c_master_bus_cleanup(struct i3c_master_controller *master)
{
int ret;
- i3c_bus_maintenance_lock(&master->bus);
- /* Disable all slave events before starting DAA. */
- ret = i3c_master_disec_locked(master, I3C_BROADCAST_ADDR,
- I3C_CCC_EVENT_SIR | I3C_CCC_EVENT_MR |
- I3C_CCC_EVENT_HJ);
- if (ret && ret != I3C_ERROR_M2)
- dev_dbg(&master->dev, "failed to send DISEC, ret=%i\n", ret);
+ i3c_gpio_switch_init(master);
- /*
- * Reset all dynamic address that may have been assigned before
- * (assigned by the bootloader for example).
- */
- ret = i3c_master_rstdaa_locked(master, I3C_BROADCAST_ADDR);
- if (ret && ret != I3C_ERROR_M2)
- dev_dbg(&master->dev, "failed to send RSTDAA, ret=%i\n", ret);
- i3c_bus_maintenance_unlock(&master->bus);
+ for(int i=0; i<4; i++) {
+ i3c_gpio_switch_dimm_group(i);
+ usleep_range(2000, 2100);
+ i3c_bus_maintenance_lock(&master->bus);
+ /* Disable all slave events before starting DAA. */
+ ret = i3c_master_disec_locked(master, I3C_BROADCAST_ADDR,
+ I3C_CCC_EVENT_SIR | I3C_CCC_EVENT_MR |
+ I3C_CCC_EVENT_HJ);
+ if (ret && ret != I3C_ERROR_M2)
+ dev_dbg(&master->dev, "failed to send DISEC, ret=%i\n", ret);
+
+ /*
+ * Reset all dynamic address that may have been assigned before
+ * (assigned by the bootloader for example).
+ */
+ ret = i3c_master_rstdaa_locked(master, I3C_BROADCAST_ADDR);
+ if (ret && ret != I3C_ERROR_M2)
+ dev_dbg(&master->dev, "failed to send RSTDAA, ret=%i\n", ret);
+
+ i3c_bus_maintenance_unlock(&master->bus);
+ usleep_range(2000, 2100);
+ }
if (master->ops->bus_cleanup)
master->ops->bus_cleanup(master);
i3c_master_detach_free_devs(master);
+
+ i3c_gpio_switch_free();
}
static void i3c_master_attach_boardinfo(struct i3c_dev_desc *i3cdev)
diff --git a/include/linux/i3c/master.h b/include/linux/i3c/master.h
index 22bcf638e5b1..6bf882d21a1e 100644
--- a/include/linux/i3c/master.h
+++ b/include/linux/i3c/master.h
@@ -690,4 +690,15 @@ void i3c_master_queue_ibi(struct i3c_dev_desc *dev, struct i3c_ibi_slot *slot);
struct i3c_ibi_slot *i3c_master_get_free_ibi_slot(struct i3c_dev_desc *dev);
+#define SEL_CPU0_I3C_DDR_GPIO 921
+#define SEL_CPU1_I3C_DDR_GPIO 922
+#define I3C_SPD_BMC_MUX0_SEL 1004
+#define I3C_SPD_BMC_MUX0_EN 852
+#define I3C_SPD_BMC_MUX1_SEL 1005
+#define I3C_SPD_BMC_MUX1_EN 853
+#define I3C_SPD_BMC_MUX2_SEL 1006
+#define I3C_SPD_BMC_MUX2_EN 854
+#define I3C_SPD_BMC_MUX3_SEL 1007
+#define I3C_SPD_BMC_MUX3_EN 909
+
#endif /* I3C_MASTER_H */
--
2.34.1
meta-luxshare/meta-bhs/recipes-kernel/linux/linux-aspeed/0001-Force-set-pmbus-page-to-4-to-fix-Delta-PSU-reading-e.patch
Executable
+64
View File
@@ -0,0 +1,64 @@
From 44944d5fe90cd5a71b60d8393324c6a90779e635 Mon Sep 17 00:00:00 2001
From: "Chen.Zhao" <zhao.chen@luxshare-ict.com>
Date: Thu, 19 Sep 2024 17:08:07 +0800
Subject: [PATCH] Force set pmbus page to 4 to fix Delta PSU reading error
issue Because Delta PSU page command has bug. It not report error when set
page above 3. It will make pmbus logic confusion. So forece set max page to
3.
---
drivers/hwmon/pmbus/pmbus.c | 17 ++++++++++++++++-
1 file changed, 16 insertions(+), 1 deletion(-)
diff --git a/drivers/hwmon/pmbus/pmbus.c b/drivers/hwmon/pmbus/pmbus.c
index 9fa5e237a03f..2ac33333e7d2 100644
--- a/drivers/hwmon/pmbus/pmbus.c
+++ b/drivers/hwmon/pmbus/pmbus.c
@@ -78,6 +78,11 @@ static void pmbus_find_sensor_groups(struct i2c_client *client,
PMBUS_STATUS_TEMPERATURE))
info->func[0] |= PMBUS_HAVE_STATUS_TEMP;
+ /*
+ * because delta psu page commad has bug, it will make pmbus mask confusion
+ * force set pmbus mask to enable read current, voltage, fan, temperature and power
+ */
+ info->func[0] = 0x3f27d;
rv = pmbus_query_register(client, PMBUS_READ_EIN);
/* only direct format for EIN and EOUT supported */
if (rv > 0 && (rv & PB_QUERY_COMMAND_SUPPORTED) &&
@@ -97,6 +102,11 @@ static void pmbus_find_sensor_groups(struct i2c_client *client,
info->m[PSC_POWER_AVERAGE] = 1;
}
+ /*
+ * because delta psu page commad has bug, it will make pmbus mask confusion.
+ * remove read other page information.
+ */
+ #if 0
/* Sensors detected on all pages */
for (page = 0; page < info->pages; page++) {
if (pmbus_check_word_register(client, page, PMBUS_READ_VOUT)) {
@@ -114,6 +124,7 @@ static void pmbus_find_sensor_groups(struct i2c_client *client,
if (pmbus_check_word_register(client, page, PMBUS_READ_POUT))
info->func[page] |= PMBUS_HAVE_POUT;
}
+ #endif
}
/*
@@ -135,7 +146,11 @@ static int pmbus_identify(struct i2c_client *client,
int page;
for (page = 1; page < PMBUS_PAGES; page++) {
- if (pmbus_set_page(client, page, 0xff) < 0)
+ /*
+ * because delta psu page commad has bug, it will make pmbus mask confusion
+ * force set max page to 4.
+ */
+ if ((pmbus_set_page(client, page, 0xff) < 0) || (page > 3))
break;
}
pmbus_set_page(client, 0, 0xff);
--
2.25.1
meta-luxshare/meta-bhs/recipes-kernel/linux/linux-aspeed/0001-Modify-JTAG-driver-to-aspeed-driver.patch
Executable
+2622
View File
File diff suppressed because it is too large Load Diff
meta-luxshare/meta-bhs/recipes-kernel/linux/linux-aspeed/0001-Solve-the-do_daa-exception-exit-issue-when-the-DIMM-.patch
Executable
+70
View File
@@ -0,0 +1,70 @@
From 459fdb4b3f4d905072f1dfa25e90deee1347779b Mon Sep 17 00:00:00 2001
From: wangjue <jue.wang2@luxshare-ict.com>
Date: Wed, 22 Oct 2025 10:48:26 +0800
Subject: [PATCH] Solve the do_daa exception exit issue when the DIMM slots are
not fully populated.
Signed-off-by: wangjue <jue.wang2@luxshare-ict.com>
---
drivers/i3c/master.c | 8 ++++++++
drivers/i3c/master/dw-i3c-master.c | 4 ++--
2 files changed, 10 insertions(+), 2 deletions(-)
diff --git a/drivers/i3c/master.c b/drivers/i3c/master.c
index 9cd566d3928f..6997a92ac8e7 100644
--- a/drivers/i3c/master.c
+++ b/drivers/i3c/master.c
@@ -1979,6 +1979,7 @@ i3c_master_register_new_i3c_devs(struct i3c_master_controller *master)
int i3c_master_do_daa(struct i3c_master_controller *master)
{
int ret = 0;
+ bool result = false;
i3c_gpio_switch_init(master);
mutex_lock(&master->daa_lock);
@@ -1989,13 +1990,20 @@ int i3c_master_do_daa(struct i3c_master_controller *master)
usleep_range(2000, 2100);
ret = i3c_master_sethid_locked(master);
ret = i3c_master_setaasa_locked(master);
+ if(ret == 0)
+ result = true;
usleep_range(2000, 2100);
}
+ if(result)
+ ret = 0;
} else {
ret = master->ops->do_daa(master);
}
i3c_bus_maintenance_unlock(&master->bus);
+ dev_dbg(&master->dev,
+ "ret = %d, result = %d\n", ret, (int)result);
+
if (ret)
goto mutex_unlock;
diff --git a/drivers/i3c/master/dw-i3c-master.c b/drivers/i3c/master/dw-i3c-master.c
index c29c609510e7..d27b89318df2 100644
--- a/drivers/i3c/master/dw-i3c-master.c
+++ b/drivers/i3c/master/dw-i3c-master.c
@@ -3162,7 +3162,7 @@ static int dw_i3c_probe(struct platform_device *pdev)
master->maxdevs = DEVICE_ADDR_TABLE_DEPTH(ret);
master->dat_depth = DEVICE_ADDR_TABLE_DEPTH(ret);
if (master->maxdevs < MAX_DEVS) {
- dev_info(master->dev, "HW DAT supports only %i target devices - enabling SW DAT to support %i devices\n",
+ dev_dbg(master->dev, "HW DAT supports only %i target devices - enabling SW DAT to support %i devices\n",
master->maxdevs, MAX_DEVS);
master->maxdevs = MAX_DEVS;
master->sw_dat_enabled = true;
@@ -3215,7 +3215,7 @@ static int dw_i3c_probe(struct platform_device *pdev)
if (ret)
dev_warn(master->dev, "Failed to initialize debug FS, ret=%i\n", ret);
- dev_info(&pdev->dev, "i3c bus %d registered, irq %d\n",
+ dev_dbg(&pdev->dev, "i3c bus %d registered, irq %d\n",
master->base.bus_id, irq);
return 0;
--
2.34.1
meta-luxshare/meta-bhs/recipes-kernel/linux/linux-aspeed/0001-Workaround-VW-interrupt-design-issue.patch
Executable
+125
View File
@@ -0,0 +1,125 @@
From 91773622d78c8a32c5591a8d1e7f9f4cb51486d8 Mon Sep 17 00:00:00 2001
From: Sujoy Ray <sujoy.ray@intel.com>
Date: Wed, 20 Mar 2024 14:22:49 -0700
Subject: [PATCH] Workaround VW interrupt design issue
In AST2600, eSPI reset interrupt is triggered at both edges.
In the ISR GPIO direction register is set, and it has been found
that if it is set after the first interrupt, it gets cleared when
the 2nd edge arrives. To fix the issue workqueue is created at it
is delayed by 500ms. The GPIO direction register is set in the
context of delayed workqueue.
Signed-off-by: Sujoy Ray <sujoy.ray@intel.com>
---
drivers/gpio/gpio-aspeed-espi-vw.c | 52 ++++++++++++++++++++++++------
1 file changed, 43 insertions(+), 9 deletions(-)
diff --git a/drivers/gpio/gpio-aspeed-espi-vw.c b/drivers/gpio/gpio-aspeed-espi-vw.c
index 0c78d78fa540..418dc7266662 100644
--- a/drivers/gpio/gpio-aspeed-espi-vw.c
+++ b/drivers/gpio/gpio-aspeed-espi-vw.c
@@ -6,6 +6,8 @@
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
+#include <linux/workqueue.h>
+#include <linux/timer.h>
#include <linux/mfd/syscon.h>
#include <linux/soc/aspeed/aspeed-espi.h>
@@ -49,6 +51,15 @@ struct aspeed_espi_gpio {
spinlock_t lock;
};
+struct aspeed_espi_vw_delayed_work_struct {
+ struct delayed_work delayed_work;
+ void *arg;
+};
+
+static struct workqueue_struct *aspeed_espi_gpio_workqueue;
+static void aspeed_espi_vw_gpio_workqueue(struct work_struct *work);
+static struct aspeed_espi_vw_delayed_work_struct aspeed_vw_work;
+
static void aspeed_espi_vw_gpio_enable(struct regmap *map, u32 dir_mask)
{
regmap_update_bits(map, ASPEED_ESPI_INT_EN, ASPEED_ESPI_INT_EN_VW_MASK,
@@ -75,6 +86,26 @@ static void set_nth_bit(u32 *n, uint8_t offset, u32 val)
*n = *n | (1ul << offset);
}
+void aspeed_espi_vw_gpio_workqueue(struct work_struct *work)
+{
+ struct aspeed_espi_gpio *gpio;
+ struct aspeed_espi_vw_delayed_work_struct *work_ptr;
+ unsigned long flags;
+
+ struct delayed_work *dw = container_of(work, struct delayed_work, work);
+
+ work_ptr = container_of(dw, struct aspeed_espi_vw_delayed_work_struct,
+ delayed_work);
+ gpio = work_ptr->arg;
+ aspeed_espi_vw_gpio_enable(gpio->map, gpio->dir_mask);
+ dev_dbg(gpio->dev, "Resetting VGPIO value [%08X] from workqueue\n",
+ cached_reg_val);
+ spin_lock_irqsave(&gpio->lock, flags);
+ regmap_update_bits(gpio->map, ASPEED_ESPI_VW_GPIO_VAL, gpio->dir_mask,
+ cached_reg_val);
+ spin_unlock_irqrestore(&gpio->lock, flags);
+}
+
static int vgpio_get_value(struct gpio_chip *gc, unsigned int offset)
{
struct aspeed_espi_gpio *gpio = gpiochip_get_data(gc);
@@ -213,22 +244,16 @@ static int aspeed_espi_vw_gpio_init(struct device *dev, struct aspeed_espi_gpio
static void aspeed_espi_vw_irq(int irq, void *arg)
{
struct aspeed_espi_gpio *gpio = arg;
- unsigned long flags;
u32 sts;
-
if (regmap_read(gpio->map, ASPEED_ESPI_INT_STS, &sts)) {
dev_dbg(gpio->dev, "Error reading int status\n");
return;
}
if (sts & ASPEED_ESPI_INT_STS_HW_RESET) {
- dev_dbg(gpio->dev, "Resetting VGPIO value [%08X]\n", cached_reg_val);
- aspeed_espi_vw_gpio_enable(gpio->map, gpio->dir_mask);
-
- spin_lock_irqsave(&gpio->lock, flags);
- regmap_update_bits(gpio->map, ASPEED_ESPI_VW_GPIO_VAL, gpio->dir_mask,
- cached_reg_val);
- spin_unlock_irqrestore(&gpio->lock, flags);
+ dev_dbg(gpio->dev, "Scheduling workqueue for deferred processing\n");
+ queue_delayed_work(aspeed_espi_gpio_workqueue, &aspeed_vw_work.delayed_work,
+ msecs_to_jiffies(500));
}
/* Clearing of status register will be done from parent driver*/
}
@@ -257,6 +282,14 @@ static int aspeed_espi_gpio_probe(struct platform_device *pdev)
aspeed_espi_register_gpio(pdev->dev.parent, aspeed_espi_vw_irq, gpio);
+ aspeed_espi_gpio_workqueue = create_workqueue("aspeed_espi_workqueue");
+ if (!aspeed_espi_gpio_workqueue) {
+ pr_err("Failed to create workqueue");
+ return -ENOMEM;
+ }
+
+ aspeed_vw_work.arg = gpio;
+ INIT_DELAYED_WORK(&aspeed_vw_work.delayed_work, aspeed_espi_vw_gpio_workqueue);
return ret;
}
@@ -265,6 +298,7 @@ static int aspeed_espi_gpio_remove(struct platform_device *pdev)
struct aspeed_espi_gpio *gpio = dev_get_drvdata(&pdev->dev);
aspeed_espi_vw_gpio_disable(gpio->map);
+ cancel_delayed_work_sync(&aspeed_vw_work.delayed_work);
return 0;
}
--
2.25.1
meta-luxshare/meta-bhs/recipes-kernel/linux/linux-aspeed/0001-soc-aspeed-abr-Add-sysfs-attrs-for-flash-toggle.patch
Executable
+223
View File
@@ -0,0 +1,223 @@
From 674e059d34193930cd48df8fe1f2f5bf49c83469 Mon Sep 17 00:00:00 2001
From: roly <Rolyli.Li@luxshare-ict.com>
Date: Thu, 9 Jan 2025 08:54:00 +0800
Subject: [PATCH] soc aspeed abr Add sysfs attrs for flash toggle
---
drivers/spi/spi-aspeed-smc.c | 60 +++++++++++++
include/linux/soc/aspeed/aspeed-abr.h | 118 ++++++++++++++++++++++++++
2 files changed, 178 insertions(+)
create mode 100644 include/linux/soc/aspeed/aspeed-abr.h
diff --git a/drivers/spi/spi-aspeed-smc.c b/drivers/spi/spi-aspeed-smc.c
index 70c4e6e3e2e8..8a819f8f65ba 100644
--- a/drivers/spi/spi-aspeed-smc.c
+++ b/drivers/spi/spi-aspeed-smc.c
@@ -13,6 +13,7 @@
#include <linux/platform_device.h>
#include <linux/spi/spi.h>
#include <linux/spi/spi-mem.h>
+#include <linux/soc/aspeed/aspeed-abr.h>
#define DEVICE_NAME "spi-aspeed-smc"
@@ -110,6 +111,53 @@ struct aspeed_spi {
u8 *op_buf;
};
+static ssize_t access_primary_show(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+ struct aspeed_spi *aspi = dev_get_drvdata(dev);
+
+ return _access_primary_show(aspi->regs, attr, buf);
+}
+
+static ssize_t access_primary_store(struct device *dev,
+ struct device_attribute *attr,
+ const char *buf, size_t size)
+{
+ struct aspeed_spi *aspi = dev_get_drvdata(dev);
+
+ return _access_primary_store(aspi->regs, attr, buf, size);
+}
+
+static ssize_t access_backup_show(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+ struct aspeed_spi *aspi = dev_get_drvdata(dev);
+
+ return _access_backup_show(aspi->regs, attr, buf);
+}
+
+static ssize_t access_backup_store(struct device *dev,
+ struct device_attribute *attr,
+ const char *buf, size_t size)
+{
+ struct aspeed_spi *aspi = dev_get_drvdata(dev);
+
+ return _access_backup_store(aspi->regs, attr, buf, size);
+}
+
+static DEVICE_ATTR_RW(access_primary);
+static DEVICE_ATTR_RW(access_backup);
+
+static struct attribute *bswitch_primary_attrs[] = {
+ &dev_attr_access_primary.attr, NULL
+};
+
+static struct attribute *bswitch_backup_attrs[] = {
+ &dev_attr_access_backup.attr, NULL
+};
+
+ATTRIBUTE_GROUPS(bswitch_primary);
+ATTRIBUTE_GROUPS(bswitch_backup);
static u32 aspeed_spi_get_io_mode(const struct spi_mem_op *op)
{
switch (op->data.buswidth) {
@@ -908,6 +956,18 @@ static int aspeed_spi_probe(struct platform_device *pdev)
ctlr->num_chipselect = data->max_cs;
ctlr->dev.of_node = dev->of_node;
+ if (of_device_is_compatible(dev->of_node, "aspeed,ast2600-fmc")) {
+ /* if boot from alt source, show access_primary, otherwise show access_backup */
+ if (readl(aspi->regs + OFFSET_ABR_CTRL_STATUS) &
+ ABR_BOOT_SRC_INDICATE) {
+ if (devm_device_add_groups(dev, bswitch_primary_groups))
+ dev_warn(dev, "Could not add access_primary\n");
+ } else {
+ if (devm_device_add_groups(dev, bswitch_backup_groups))
+ dev_warn(dev, "Could not add access_backup\n");
+ }
+ }
+
ret = devm_spi_register_controller(dev, ctlr);
if (ret) {
dev_err(&pdev->dev, "spi_register_controller failed\n");
diff --git a/include/linux/soc/aspeed/aspeed-abr.h b/include/linux/soc/aspeed/aspeed-abr.h
new file mode 100644
index 000000000000..144f43dff1ac
--- /dev/null
+++ b/include/linux/soc/aspeed/aspeed-abr.h
@@ -0,0 +1,118 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+
+#ifndef __ASPEED_ABR_H__
+#define __ASPEED_ABR_H__
+
+#include <linux/device.h>
+#include <linux/sysfs.h>
+#include <linux/io.h>
+
+#define OFFSET_ABR_CTRL_STATUS 0x64
+#define OFFSET_ABR_TIMER_RELOAD 0x68
+#define OFFSET_ABR_TIMER_RESTART 0x6c
+
+#define ABR_WDT_ENABLE BIT(0)
+#define ABR_BOOT_SRC_INDICATE BIT(4)
+#define ABR_RESTART_MAGIC 0x4755
+#define ABR_CLEAR_BOOT_SRC_MAGIC (0xEA << 16)
+#define ABR_RELOAD_MAX_VALUE 0x1fff
+
+static inline ssize_t _access_primary_show(void __iomem *regs,
+ struct device_attribute *attr,
+ char *buf)
+{
+ u32 status = readl(regs + OFFSET_ABR_CTRL_STATUS);
+
+ return sysfs_emit(buf, "%u\n", !(status & ABR_BOOT_SRC_INDICATE));
+}
+
+static inline ssize_t _access_primary_store(void __iomem *regs,
+ struct device_attribute *attr,
+ const char *buf, size_t size)
+{
+ unsigned long val;
+
+ if (kstrtoul(buf, 10, &val))
+ return -EINVAL;
+
+ /* disable watchdog */
+ if (val == 0) {
+ writel(0, regs + OFFSET_ABR_CTRL_STATUS);
+ return size;
+ }
+
+ /* val is the microsecond, convert to reload count(0.1s) */
+ val /= (100 * 1000);
+
+ /*
+ * bit[12:0] : Reload value of expire time
+ * The time unit is 0.1 second. Default set at 22 seconds
+ * 0: Immediately timeout
+ */
+ val = val < ABR_RELOAD_MAX_VALUE ? val : ABR_RELOAD_MAX_VALUE;
+
+ writel(0, regs + OFFSET_ABR_CTRL_STATUS);
+ writel(val, regs + OFFSET_ABR_TIMER_RELOAD);
+
+ /* Write 0x4755 value to load the reload value into watchdog counter */
+ writel(ABR_RESTART_MAGIC, regs + OFFSET_ABR_TIMER_RESTART);
+
+ /* Enable watchdog */
+ writel(ABR_WDT_ENABLE, regs + OFFSET_ABR_CTRL_STATUS);
+ return size;
+}
+
+static inline ssize_t _access_backup_show(void __iomem *regs,
+ struct device_attribute *attr,
+ char *buf)
+{
+ u32 status = readl(regs + OFFSET_ABR_CTRL_STATUS);
+ u32 timer_reload = readl(regs + OFFSET_ABR_TIMER_RELOAD);
+
+ if (!(status & ABR_WDT_ENABLE))
+ return sysfs_emit(buf, "%u\n", 0);
+
+ /*
+ * [31:16] Counter value status
+ * timeout unit is 0.1s, convert to microseconds
+ */
+ return sysfs_emit(buf, "%u\n", (timer_reload >> 16) * 100 * 1000);
+}
+
+static inline ssize_t _access_backup_store(void __iomem *regs,
+ struct device_attribute *attr,
+ const char *buf, size_t size)
+{
+ unsigned long val;
+
+ if (kstrtoul(buf, 10, &val))
+ return -EINVAL;
+
+ /* disable watchdog */
+ if (val == 0) {
+ writel(0, regs + OFFSET_ABR_CTRL_STATUS);
+ return size;
+ }
+
+ /* val is the microsecond, convert to reload count(0.1s) */
+ val /= (100 * 1000);
+
+ /*
+ * bit[12:0] : Reload value of expire time
+ * The time unit is 0.1 second. Default set at 22 seconds
+ * 0: Immediately timeout
+ */
+ val = val < ABR_RELOAD_MAX_VALUE ? val : ABR_RELOAD_MAX_VALUE;
+
+ writel(0, regs + OFFSET_ABR_CTRL_STATUS);
+ writel(val, regs + OFFSET_ABR_TIMER_RELOAD);
+
+ /* Write 0x4755 value to load the reload value into watchdog counter */
+ writel(ABR_RESTART_MAGIC, regs + OFFSET_ABR_TIMER_RESTART);
+
+ /* Enable watchdog */
+ writel(ABR_WDT_ENABLE, regs + OFFSET_ABR_CTRL_STATUS);
+ return size;
+}
+
+#endif
--
2.25.1
meta-luxshare/meta-bhs/recipes-kernel/linux/linux-aspeed/0002-i3c-mctp-workaround-for-wrong-DCR-value.patch
Executable
+32
View File
@@ -0,0 +1,32 @@
From f9583e98c2a73f1642c28dc7c043bc8a656c6b83 Mon Sep 17 00:00:00 2001
From: Zbigniew Lukwinski <zbigniew.lukwinski@linux.intel.com>
Date: Wed, 11 May 2022 15:26:24 +0200
Subject: [PATCH] i3c: mctp: workaround for wrong DCR value
In GNR A0 there is an issue about DCR value. I3C MNG IP in GNR A0
introduces itself with DCR=0xC9. Adding this value to allow MCTP over
I3C driver to be loaded in this case as well.
Issue will be fixed in GNR B0.
Signed-off-by: Zbigniew Lukwinski <zbigniew.lukwinski@linux.intel.com>
Upstream-Status: Pending
---
drivers/i3c/mctp/i3c-mctp.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/i3c/mctp/i3c-mctp.c b/drivers/i3c/mctp/i3c-mctp.c
index b0e3814..42e864d 100644
--- a/drivers/i3c/mctp/i3c-mctp.c
+++ b/drivers/i3c/mctp/i3c-mctp.c
@@ -333,6 +333,8 @@ static void i3c_mctp_remove(struct i3c_device *i3cdev)
static const struct i3c_device_id i3c_mctp_ids[] = {
I3C_CLASS(0xCC, 0x0),
+ /* Workaround for GNR A0 where I3C MNG IP introduces itself with DCR=0xC9 */
+ I3C_CLASS(0xC9, 0x0),
{ },
};
--
2.7.4
meta-luxshare/meta-bhs/recipes-kernel/linux/linux-aspeed/0003-Revert-pwm-Drop-support-for-legacy-drivers.patch
Executable
+105
View File
@@ -0,0 +1,105 @@
diff --git a/drivers/pwm/core.c b/drivers/pwm/core.c
index d333e7422f4a..f586deaf9d38 100644
--- a/drivers/pwm/core.c
+++ b/drivers/pwm/core.c
@@ -236,7 +236,14 @@ EXPORT_SYMBOL_GPL(pwm_get_chip_data);
static bool pwm_ops_check(const struct pwm_chip *chip)
{
const struct pwm_ops *ops = chip->ops;
+ /* driver supports legacy, non-atomic operation */
+ if (ops->config && ops->enable && ops->disable) {
+ if (IS_ENABLED(CONFIG_PWM_DEBUG))
+ dev_warn(chip->dev,
+ "Driver needs updating to atomic API\n");
+ return true;
+ }
if (!ops->apply)
return false;
@@ -538,6 +545,73 @@ static void pwm_apply_state_debug(struct pwm_device *pwm,
}
}
+static int pwm_apply_legacy(struct pwm_chip *chip, struct pwm_device *pwm,
+ const struct pwm_state *state)
+{
+ int err;
+ struct pwm_state initial_state = pwm->state;
+
+ if (state->polarity != pwm->state.polarity) {
+ if (!chip->ops->set_polarity)
+ return -EINVAL;
+
+ /*
+ * Changing the polarity of a running PWM is only allowed when
+ * the PWM driver implements ->apply().
+ */
+ if (pwm->state.enabled) {
+ chip->ops->disable(chip, pwm);
+
+ /*
+ * Update pwm->state already here in case
+ * .set_polarity() or another callback depend on that.
+ */
+ pwm->state.enabled = false;
+ }
+
+ err = chip->ops->set_polarity(chip, pwm, state->polarity);
+ if (err)
+ goto rollback;
+
+ pwm->state.polarity = state->polarity;
+ }
+
+ if (!state->enabled) {
+ if (pwm->state.enabled)
+ chip->ops->disable(chip, pwm);
+
+ return 0;
+ }
+
+ /*
+ * We cannot skip calling ->config even if state->period ==
+ * pwm->state.period && state->duty_cycle == pwm->state.duty_cycle
+ * because we might have exited early in the last call to
+ * pwm_apply_state because of !state->enabled and so the two values in
+ * pwm->state might not be configured in hardware.
+ */
+ err = chip->ops->config(pwm->chip, pwm,
+ state->duty_cycle,
+ state->period);
+ if (err)
+ goto rollback;
+
+ pwm->state.period = state->period;
+ pwm->state.duty_cycle = state->duty_cycle;
+
+ if (!pwm->state.enabled) {
+ err = chip->ops->enable(chip, pwm);
+ if (err)
+ goto rollback;
+ }
+
+ return 0;
+
+rollback:
+ pwm->state = initial_state;
+ return err;
+}
+
/**
* pwm_apply_state() - atomically apply a new state to a PWM device
* @pwm: PWM device
@@ -570,7 +644,10 @@ int pwm_apply_state(struct pwm_device *pwm, const struct pwm_state *state)
state->usage_power == pwm->state.usage_power)
return 0;
- err = chip->ops->apply(chip, pwm, state);
+ if (chip->ops->apply)
+ err = chip->ops->apply(chip, pwm, state);
+ else
+ err = pwm_apply_legacy(chip, pwm, state);
if (err)
return err;
meta-luxshare/meta-bhs/recipes-kernel/linux/linux-aspeed/0003-i3c-master-drop-GETMRL-and-GETMWL-for-MNG-use-case.patch
Executable
+36
View File
@@ -0,0 +1,36 @@
From 356d9bdcc0555170ae8f61bae3d082745a5b7406 Mon Sep 17 00:00:00 2001
From: Zbigniew Lukwinski <zbigniew.lukwinski@linux.intel.com>
Date: Fri, 11 Aug 2023 01:16:51 +0200
Subject: [PATCH] i3c: master: drop GETMRL and GETMWL for MNG use case
For MNG use case there is no need to send GETMRL and GETMWL because those
CCCs are not supported by target device. For MNG use case will use
hardcoded maximum values.
Moreover there is an issue in ICE1.0 where PEC error counter is bumped up
in case sending not supported CCC.
Signed-off-by: Zbigniew Lukwinski <zbigniew.lukwinski@linux.intel.com>
---
drivers/i3c/master.c | 6 ++++--
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers/i3c/master.c b/drivers/i3c/master.c
index 234599825f41..0f9fcf1fab35 100644
--- a/drivers/i3c/master.c
+++ b/drivers/i3c/master.c
@@ -1546,8 +1546,10 @@ static int i3c_master_retrieve_dev_info(struct i3c_dev_desc *dev)
if (dev->info.bcr & I3C_BCR_IBI_PAYLOAD)
dev->info.max_ibi_len = 1;
- i3c_master_getmrl_locked(master, &dev->info);
- i3c_master_getmwl_locked(master, &dev->info);
+ if (!master->is_mng) {
+ i3c_master_getmrl_locked(master, &dev->info);
+ i3c_master_getmwl_locked(master, &dev->info);
+ }
if (dev->info.bcr & I3C_BCR_HDR_CAP) {
ret = i3c_master_gethdrcap_locked(master, &dev->info);
--
2.34.1
meta-luxshare/meta-bhs/recipes-kernel/linux/linux-aspeed/0004-Add-I3C-GPIO-switch-in-dw-i3c-master-driver.patch
Executable
+89
View File
@@ -0,0 +1,89 @@
From 0851611d47f99f5bbba29d3cb39e109a4ecdcb0e Mon Sep 17 00:00:00 2001
From: wangjue <jue.wang2@luxshare-ict.com>
Date: Fri, 11 Oct 2024 12:48:24 +0800
Subject: [PATCH] Add I3C GPIO switch in dw-i3c-master driver
Signed-off-by: wangjue <jue.wang2@luxshare-ict.com>
---
drivers/i3c/master/dw-i3c-master.c | 34 ++++++++++++++++++++++++++++++
1 file changed, 34 insertions(+)
diff --git a/drivers/i3c/master/dw-i3c-master.c b/drivers/i3c/master/dw-i3c-master.c
index c29c609510e7..6d1ba40eca0f 100644
--- a/drivers/i3c/master/dw-i3c-master.c
+++ b/drivers/i3c/master/dw-i3c-master.c
@@ -25,6 +25,7 @@
#include <linux/regmap.h>
#include <linux/reset.h>
#include <linux/slab.h>
+#include <linux/gpio.h>
/*
* Below bits are valid for I3Cx Global register (REG1) on AST2600 platform.
@@ -373,6 +374,9 @@
#define AST2600_I3C_IBI_MAX_PAYLOAD 255
+#define SEL_CPU0_I3C_DDR_GPIO 921
+#define SEL_CPU1_I3C_DDR_GPIO 922
+
struct dw_i3c_master_caps {
u8 cmdfifodepth;
u8 datafifodepth;
@@ -3110,6 +3114,33 @@ static int dw_i3c_debugfs_init(struct dw_i3c_master *master)
return 0;
}
+static void i3c_gpio_switch_bmc(struct dw_i3c_master *master)
+{
+ if (gpio_request(SEL_CPU0_I3C_DDR_GPIO, "dw-i3c-master")) {
+ dev_err(master->dev, "unable to allocate SEL_CPU0_I3C_DDR_GPIO\n");
+ return;
+ }
+
+ if (gpio_request(SEL_CPU1_I3C_DDR_GPIO, "dw-i3c-master")) {
+ dev_err(master->dev, "unable to allocate SEL_CPU0_I3C_DDR_GPIO\n");
+ return;
+ }
+ gpio_direction_output(SEL_CPU0_I3C_DDR_GPIO, 1);
+ gpio_direction_output(SEL_CPU1_I3C_DDR_GPIO, 1);
+
+ usleep_range(500, 1000);
+}
+
+static void i3c_gpio_switch_bios(struct dw_i3c_master *master)
+{
+ gpio_direction_output(SEL_CPU0_I3C_DDR_GPIO, 0);
+ gpio_direction_output(SEL_CPU1_I3C_DDR_GPIO, 0);
+ usleep_range(500, 1000);
+
+ gpio_free(SEL_CPU0_I3C_DDR_GPIO);
+ gpio_free(SEL_CPU1_I3C_DDR_GPIO);
+}
+
static int dw_i3c_probe(struct platform_device *pdev)
{
const struct of_device_id *match;
@@ -3149,6 +3180,7 @@ static int dw_i3c_probe(struct platform_device *pdev)
spin_lock_init(&master->ibi.master.lock);
platform_set_drvdata(pdev, master);
+ i3c_gpio_switch_bmc(master);
/* Information regarding the FIFOs/QUEUEs depth */
ret = readl(master->regs + QUEUE_STATUS_LEVEL);
@@ -3218,9 +3250,11 @@ static int dw_i3c_probe(struct platform_device *pdev)
dev_info(&pdev->dev, "i3c bus %d registered, irq %d\n",
master->base.bus_id, irq);
+ i3c_gpio_switch_bios(master);
return 0;
err_assert_rst:
+ i3c_gpio_switch_bios(master);
reset_control_assert(master->core_rst);
err_disable_core_clk:
--
2.34.1
meta-luxshare/meta-bhs/recipes-kernel/linux/linux-aspeed/aspeed-ast2600-evb.dts
Executable
+668
View File
@@ -0,0 +1,668 @@
// SPDX-License-Identifier: GPL-2.0-or-later
// Copyright 2019 IBM Corp.
/dts-v1/;
#include "aspeed-g6.dtsi"
#include <dt-bindings/gpio/aspeed-gpio.h>
/ {
model = "AST2600 EVB";
compatible = "aspeed,ast2600-evb", "aspeed,ast2600";
aliases {
serial4 = &uart5;
i2c16 = &channel_12_0;
i2c17 = &channel_12_1;
i2c18 = &channel_12_2;
i2c19 = &channel_12_3;
i2c20 = &channel_12_4;
i2c21 = &channel_12_5;
i2c22 = &channel_12_6;
i2c23 = &channel_12_7;
};
chosen {
bootargs = "console=ttyS4,115200n8";
};
memory@80000000 {
device_type = "memory";
reg = <0x80000000 0x80000000>;
};
reserved-memory {
#address-cells = <1>;
#size-cells = <1>;
ranges;
video_engine_memory: video {
size = <0x04000000>;
alignment = <0x01000000>;
compatible = "shared-dma-pool";
reusable;
};
gfx_memory: framebuffer {
size = <0x01000000>;
alignment = <0x01000000>;
compatible = "shared-dma-pool";
reusable;
};
espi_mmbi_memory: espi_mmbi_memory {
no-map;
reg = <0x9EFF0000 0x10000>; /* 64K */
};
};
leds {
compatible = "gpio-leds";
heartbeat {
gpios = <&gpio0 ASPEED_GPIO(B, 0) GPIO_ACTIVE_LOW>;
linux,default-trigger = "timer";
};
health_green {
gpios = <&gpio0 ASPEED_GPIO(G, 6) GPIO_ACTIVE_LOW>;
};
health_red {
gpios = <&gpio0 ASPEED_GPIO(G, 7) GPIO_ACTIVE_LOW>;
};
uidbtn {
gpios = <&gpio0 ASPEED_GPIO(S, 6) GPIO_ACTIVE_LOW>;
};
};
iio-hwmon {
compatible = "iio-hwmon";
io-channels = <&adc0 0>, <&adc0 1>, <&adc0 2>, <&adc0 3>,
<&adc0 4>, <&adc0 5>, <&adc0 6>, <&adc0 7>,
<&adc1 0>, <&adc1 1>, <&adc1 2>, <&adc1 3>,
<&adc1 4>, <&adc1 5>, <&adc1 6>, <&adc1 7>;
};
};
&mdio0 {
status = "okay";
ethphy0: ethernet-phy@0 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <0>;
};
};
&mac0 {
status = "okay";
phy-mode = "rgmii-txid";
phy-handle = <&ethphy0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_rgmii1_default>;
clocks = <&syscon ASPEED_CLK_GATE_MAC1CLK>,
<&syscon ASPEED_CLK_MAC1RCLK>;
clock-names = "MACCLK", "RCLK";
};
&uart1 {
status = "okay";
pinctrl-0 = <&pinctrl_txd1_default
&pinctrl_rxd1_default>;
};
&uart2 {
status = "okay";
pinctrl-0 = <>;
};
&uart3 {
status = "okay";
pinctrl-0 = <>;
};
&uart4 {
status = "okay";
pinctrl-0 = <>;
};
&uart5 {
status = "okay";
};
&uart_routing {
status = "okay";
};
&emmc_controller {
status = "okay";
};
&emmc {
non-removable;
bus-width = <4>;
max-frequency = <100000000>;
clk-phase-mmc-hs200 = <9>, <225>;
};
&rtc {
status = "okay";
};
&fmc {
status = "okay";
flash@0 {
status = "okay";
m25p,fast-read;
label = "bmc";
spi-rx-bus-width = <2>;
spi-max-frequency = <25000000>;
#include "openbmc-flash-layout-64.dtsi"
};
flash@1 {
status = "okay";
m25p,fast-read;
label = "alt-bmc";
spi-rx-bus-width = <2>;
spi-max-frequency = <25000000>;
#include "openbmc-flash-layout-64-alt.dtsi"
};
};
&spi1 {
status = "okay";
low-spi-clk-write;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spi1_default &pinctrl_spi1cs1_default>;
flash@0 {
status = "okay";
m25p,fast-read;
label = "bios";
spi-max-frequency = <33000000>;
spi-tx-bus-width = <1>;
spi-rx-bus-width = <1>;
};
};
&adc0 {
vref = <1800>;
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_adc0_default &pinctrl_adc1_default
&pinctrl_adc2_default &pinctrl_adc3_default
&pinctrl_adc4_default &pinctrl_adc5_default
&pinctrl_adc6_default &pinctrl_adc7_default>;
};
&adc1 {
vref = <1800>;
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_adc8_default &pinctrl_adc9_default
&pinctrl_adc10_default &pinctrl_adc11_default
&pinctrl_adc12_default &pinctrl_adc13_default
&pinctrl_adc14_default &pinctrl_adc15_default>;
};
&i2c0 {
status = "okay";
};
&i2c1 {
status = "okay";
};
&i2c2 {
status = "okay";
};
&i2c3 {
status = "okay";
};
&i2c4 {
status = "okay";
};
&i2c5 {
status = "okay";
};
&i2c6 {
status = "okay";
};
&i2c7 {
status = "okay";
};
&i2c8 {
status = "okay";
};
&i2c9 {
status = "okay";
};
&i2c12 {
status = "okay";
i2c-switch@74 {
compatible = "nxp,pca9548";
reg = <0x74>;
#address-cells = <1>;
#size-cells = <0>;
channel_12_0: i2c@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
};
channel_12_1: i2c@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
};
channel_12_2: i2c@2 {
#address-cells = <1>;
#size-cells = <0>;
reg = <2>;
};
channel_12_3: i2c@3 {
#address-cells = <1>;
#size-cells = <0>;
reg = <3>;
};
channel_12_4: i2c@4 {
#address-cells = <1>;
#size-cells = <0>;
reg = <4>;
};
channel_12_5: i2c@5 {
#address-cells = <1>;
#size-cells = <0>;
reg = <5>;
};
channel_12_6: i2c@6 {
#address-cells = <1>;
#size-cells = <0>;
reg = <6>;
};
channel_12_7: i2c@7 {
#address-cells = <1>;
#size-cells = <0>;
reg = <7>;
};
};
};
&i2c13 {
status = "okay";
};
&i2c14 {
status = "okay";
eeprom@53 {
compatible = "atmel,24c32";
reg = <0x53>;
};
};
&i2c15 {
status = "okay";
};
&i3cglobal {
status = "okay";
};
&i3c0 {
/* I3C_SPD_BMC */
status = "okay";
i3c-scl-hz = <2000000>;
i3c-pp-scl-high-ns = <250>;
i2c-scl-hz = <400000>;
i3c-od-scl-high-ns = <1130>;
sda-tx-hold-ns = <30>;
jdec-spd;
spd@50,3C000000000 {
reg = <0x50 0x3C0 0x00000000>;
assigned-address = <0x50>;
};
spd@48,3C000000008 {
reg = <0x48 0x3C0 0x00000008>;
assigned-address = <0x48>;
};
spd@10,3C000000010 {
reg = <0x10 0x3C0 0x00000010>;
assigned-address = <0x10>;
};
spd@30,3C000000030 {
reg = <0x30 0x3C0 0x00000030>;
assigned-address = <0x30>;
};
spd@52,3C000000002 {
reg = <0x52 0x3C0 0x00000002>;
assigned-address = <0x52>;
};
spd@4A,3C00000000A {
reg = <0x4A 0x3C0 0x0000000A>;
assigned-address = <0x4A>;
};
spd@12,3C000000012 {
reg = <0x12 0x3C0 0x00000012>;
assigned-address = <0x12>;
};
spd@32,3C000000032 {
reg = <0x32 0x3C0 0x00000032>;
assigned-address = <0x32>;
};
spd@54,3C000000004 {
reg = <0x54 0x3C0 0x00000004>;
assigned-address = <0x54>;
};
spd@4C,3C00000000C {
reg = <0x4C 0x3C0 0x0000000C>;
assigned-address = <0x4C>;
};
spd@14,3C000000014 {
reg = <0x14 0x3C0 0x00000014>;
assigned-address = <0x14>;
};
spd@34,3C000000034 {
reg = <0x34 0x3C0 0x00000034>;
assigned-address = <0x34>;
};
};
&i3c1 {
/* I3C_SPD_BMC */
status = "okay";
i3c-scl-hz = <2000000>;
i3c-pp-scl-high-ns = <250>;
i2c-scl-hz = <400000>;
i3c-od-scl-high-ns = <1130>;
sda-tx-hold-ns = <30>;
jdec-spd;
spd@50,3C000000000 {
reg = <0x50 0x3C0 0x00000000>;
assigned-address = <0x50>;
};
spd@48,3C000000008 {
reg = <0x48 0x3C0 0x00000008>;
assigned-address = <0x48>;
};
spd@10,3C000000010 {
reg = <0x10 0x3C0 0x00000010>;
assigned-address = <0x10>;
};
spd@30,3C000000030 {
reg = <0x30 0x3C0 0x00000030>;
assigned-address = <0x30>;
};
spd@52,3C000000002 {
reg = <0x52 0x3C0 0x00000002>;
assigned-address = <0x52>;
};
spd@4A,3C00000000A {
reg = <0x4A 0x3C0 0x0000000A>;
assigned-address = <0x4A>;
};
spd@12,3C000000012 {
reg = <0x12 0x3C0 0x00000012>;
assigned-address = <0x12>;
};
spd@32,3C000000032 {
reg = <0x32 0x3C0 0x00000032>;
assigned-address = <0x32>;
};
spd@54,3C000000004 {
reg = <0x54 0x3C0 0x00000004>;
assigned-address = <0x54>;
};
spd@4C,3C00000000C {
reg = <0x4C 0x3C0 0x0000000C>;
assigned-address = <0x4C>;
};
spd@14,3C000000014 {
reg = <0x14 0x3C0 0x00000014>;
assigned-address = <0x14>;
};
spd@34,3C000000034 {
reg = <0x34 0x3C0 0x00000034>;
assigned-address = <0x34>;
};
};
&fsim0 {
status = "okay";
};
&kcs1 {
aspeed,lpc-io-reg = <0xCA0>;
status = "okay";
};
&kcs2 {
aspeed,lpc-io-reg = <0xCA8 0xCA9>;
status = "okay";
};
&kcs3 {
aspeed,lpc-io-reg = <0xCA2>;
status = "okay";
};
&kcs4 {
aspeed,lpc-io-reg = <0xCA4>;
status = "okay";
};
&vhub {
status = "okay";
pinctrl-names = "default";
};
&video {
status = "okay";
memory-region = <&video_engine_memory>;
};
&gfx {
status = "okay";
memory-region = <&gfx_memory>;
};
&espi {
status = "okay";
};
&vwgpio {
gpio-count = <32>;
gpio-names-mask = <0x000001F3>;
gpio-dir-mask = <0x00000FF0>;
gpio-names = "VW_FM_BIOS_POST_CMPLT_N", "VW_DIMM_I3C_SWITCH",
"VW_FM_DUAL_PARTITION_N", "VW_FM_STANDALONE_MODE_N",
"VW_FM_4S_8S_N_MODE", "VW_FM_NODE_ID_1", "VW_FM_NODE_ID_0";
status = "okay";
};
&mmbi {
status = "okay";
host-map-addr = <0xF6810000>;
memory-region = <&espi_mmbi_memory>;
};
&sio_regs {
status = "okay";
sio_status {
offset = <0x10C>;
bit-mask = <0x1F>;
bit-shift = <4>;
};
sio29_status {
offset = <0x170>;
bit-mask = <0xFF>;
bit-shift = <8>;
};
};
&lpc_sio {
status = "okay";
};
&lpc_snoop {
snoop-ports = <0x80>;
status = "okay";
};
//&peci0 {
// status = "okay";
//};
&jtag0 {
status = "okay";
};
&jtag1 {
status = "okay";
};
&wdt2 {
status = "okay";
};
&pwm_tacho {
status = "okay";
pinctrl-names = "default";
#pwm-cells=<3>;
pinctrl-0 = <&pinctrl_pwm0_default &pinctrl_tach0_default
&pinctrl_pwm1_default &pinctrl_tach1_default
&pinctrl_pwm2_default &pinctrl_tach2_default
&pinctrl_pwm3_default &pinctrl_tach3_default
&pinctrl_pwm4_default &pinctrl_tach4_default
&pinctrl_pwm5_default &pinctrl_tach5_default
&pinctrl_pwm6_default &pinctrl_tach6_default
&pinctrl_pwm7_default &pinctrl_tach7_default
>;
fan@0 {
reg = <0x00>;
aspeed,fan-tach-ch = /bits/ 8 <0x00>;
};
fan@1 {
reg = <0x01>;
aspeed,fan-tach-ch = /bits/ 8 <0x01>;
};
fan@2 {
reg = <0x02>;
aspeed,fan-tach-ch = /bits/ 8 <0x02>;
};
fan@3 {
reg = <0x03>;
aspeed,fan-tach-ch = /bits/ 8 <0x03>;
};
fan@4 {
reg = <0x04>;
aspeed,fan-tach-ch = /bits/ 8 <0x04>;
};
fan@5 {
reg = <0x05>;
aspeed,fan-tach-ch = /bits/ 8 <0x05>;
};
fan@6 {
reg = <0x06>;
aspeed,fan-tach-ch = /bits/ 8 <0x06>;
};
fan@7 {
reg = <0x07>;
aspeed,fan-tach-ch = /bits/ 8 <0x07>;
};
};
&mctp {
status = "okay";
};
&peci_legacy0 {
status = "okay";
};
&pcieh {
status = "okay";
};
&gpio0 {
status = "okay";
gpio-line-names =
/*A0-A7*/ "","","","","SMB_CPU_PIROM_SCL","SMB_CPU_PIROM_SDA","SMB_IPMB_STBY_LVC3_SCL","SMB_IPMB_STBY_LVC3_SDA",
/*B0-B7*/ "","","","FM_CPU1_ERR2_LVT3_N","RGMII_BMC_RMM4_LVC3_R_MDC","RGMII_BMC_RMM4_LVC3_R_MDIO","FM_BMC_BMCINIT_R","FP_ID_LED_N",
/*C0-C7*/ "FM_FORCE_BMC_UPDATE_N","RST_RGMII_PHYRST_N","FM_TPM_EN_PULSE","","","","FM_CPU1_ERR0_LVT3_N","FM_CPU1_ERR1_LVT3_N",
/*D0-D7*/ "CPU_ERR0","CPU_ERR1","CPU_ERR2","PRDY_N","FM_SPD_SWITCH_CTRL_N","","","",
/*E0-E7*/ "FM_SKT1_FAULT_LED","FM_SKT0_FAULT_LED","CLK_50M_CKMNG_BMCB","","I3C_SPD_BMC_MUX0_EN","I3C_SPD_BMC_MUX1_EN","I3C_SPD_BMC_MUX2_EN","",
/*F0-F7*/ "","FM_DUAL_PARTITION_MODE_N","FM_STANDALONE_MODE_N","FM_4S_8S_N_MODE","FM_NODE_ID0","FM_NODE_ID1","","",
/*G0-G7*/ "FM_SMB_BMC_NVME_LVC3_ALERT_N","RST_BMC_HSBP_MUX_N","FP_LED_STATUS_GREEN_N","FP_LED_STATUS_AMBER_N","","FM_PARTITION_SEL","","",
/*H0-H7*/ "POWER_OUT","SGPIO_BMC_LD_R","SGPIO_BMC_DOUT_R","SGPIO_BMC_DIN","PLTRST_N","CPU_CATERR","","",
/*I0-I7*/ "","JTAG_ASD_TDI_R","JTAG_ASD_TCK_R","JTAG_ASD_TMS_R","JTAG_ASD_TDO","FM_BMC_PWRBTN_OUT_R_N","FM_BMC_PWR_BTN_N","",
/*J0-J7*/ "","","","","","","","",
/*K0-K7*/ "","","","","","","","",
/*L0-L7*/ "","","","","PREQ_N","I3C_SPD_BMC_MUX3_EN","","",
/*M0-M7*/ "","","","","","","SPA_SOUT","SPA_SIN",
/*N0-N7*/ "","SEL_CPU0_I3C_DDR_SW","SEL_CPU1_I3C_DDR_SW","","ID_BUTTON","POWER_BUTTON","SPB_SOUT","SPB_SIN",
/*O0-O7*/ "","","","","","","NMI_BUTTON","SPEAKER_BMC_R",
/*P0-P7*/ "","","","","","","","LED_BMC_HB_LED_N",
/*Q0-Q7*/ "","","","","","","","",
/*R0-R7*/ "","","","","","","","",
/*S0-S7*/ "RST_BMC_PCIE_MUX_N","FM_BMC_TRUST_N","FM_BMC_FRU_WP_N","","PWRGD_CPU0_AUXPWRGD","","","EN_BMC_ADC_P3V_VBAT",
/*T0-T7*/ "","","","","","","","",
/*U0-U7*/ "","","","","","","","",
/*V0-V7*/ "SIO_S3","SIO_S5","","SIO_ONCONTROL","","PS_PWROK","","",
/*W0-W7*/ "LPC_LAD0_ESPI_R_IO0","LPC_LAD1_ESPI_R_IO1","LPC_LAD2_ESPI_R_IO2","LPC_LAD3_ESPI_R_IO3","CLK_24M_66M_LPC0_ESPI_BMC","LPC_LFRAME_N_ESPI_CS0_BMC_N","IRQ_LPC_SERIRQ_ESPI_ALERT_N","RST_LPC_LRST_ESPI_RST_BMC_R_N",
/*X0-X7*/ "SEL_MONITOR_MUX","","PCH_BMC_THERMTRIP","","I3C_SPD_BMC_MUX0_SEL","I3C_SPD_BMC_MUX1_SEL","I3C_SPD_BMC_MUX2_SEL","I3C_SPD_BMC_MUX3_SEL",
/*Y0-Y7*/ "FM_BMC_CMOS_CLR_R_N","","FM_BMC_SAFS_EN","IRQ_SML1_PMBUS_BMC_ALERT_N","SPI_BMC_BOOT_R_IO2","SPI_BMC_BOOT_R_IO3","PU_SPI_BMC_BOOT_ABR","PU_SPI_BMC_BOOT_WP_N",
/*Z0-Z7*/ "","","","HW_STRAP_5","HW_STRAP_6","HW_STRAP_7","HW_STRAP_2","HW_STRAP_3";
};
meta-luxshare/meta-bhs/recipes-kernel/linux/linux-aspeed/enable-gpio-key.cfg
Executable
+4
View File
@@ -0,0 +1,4 @@
CONFIG_INPUT_EVDEV=y
CONFIG_INPUT_KEYBOARD=y
CONFIG_KEYBOARD_GPIO=y
CONFIG_KEYBOARD_GPIO_POLLED=y
meta-luxshare/meta-bhs/recipes-kernel/linux/linux-aspeed/enable-jtag-driver.cfg
Executable
+2
View File
@@ -0,0 +1,2 @@
CONFIG_JTAG=y
CONFIG_JTAG_ASPEED=y
meta-luxshare/meta-bhs/recipes-kernel/linux/linux-aspeed/intel-bhs.cfg
Executable
+8
View File
@@ -0,0 +1,8 @@
CONFIG_ESPI_LGMR_ADDR=0xF6810000
CONFIG_SENSORS_ASPEED_CHASSIS=y
CONFIG_GPIO_ASPEED_ESPI_VW=y
CONFIG_SMART_MODULE=n
CONFIG_DW_I3C_MASTER=m
CONFIG_MODULES=y
CONFIG_MODULE_UNLOAD=y
meta-luxshare/meta-bhs/recipes-kernel/linux/linux-aspeed_%.bbappend
Executable
+28
View File
@@ -0,0 +1,28 @@
FILESEXTRAPATHS:prepend := "${THISDIR}/${PN}:"
SRC_URI += " \
file://intel-bhs.cfg \
file://aspeed-ast2600-evb.dts \
file://0001-Workaround-VW-interrupt-design-issue.patch \
file://0002-i3c-mctp-workaround-for-wrong-DCR-value.patch \
file://0003-i3c-master-drop-GETMRL-and-GETMWL-for-MNG-use-case.patch \
file://0001-Force-set-pmbus-page-to-4-to-fix-Delta-PSU-reading-e.patch \
file://0003-Revert-pwm-Drop-support-for-legacy-drivers.patch \
file://0001-Modify-JTAG-driver-to-aspeed-driver.patch \
file://enable-gpio-key.cfg \
file://enable-jtag-driver.cfg \
file://0001-soc-aspeed-abr-Add-sysfs-attrs-for-flash-toggle.patch \
file://0001-Add-sw-workaround-to-let-all-dimm-spd-devices-to-rec.patch \
file://0001-Solve-the-do_daa-exception-exit-issue-when-the-DIMM-.patch \
"
do_configure:append() {
dts="../aspeed-ast2600-evb.dts"
if [ ! -f $dts]; then
echo $dts" does not exist"
else
cp ../aspeed-ast2600-evb.dts ./source/arch/arm/boot/dts/
fi
}