Initial commit
This commit is contained in:
Your Name
@@ -0,0 +1,127 @@
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{
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||||
"name": "p10bmc",
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"version": "A3",
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"data_region": {
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"patch": true,
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||||
"ecc_region": true,
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||||
"key": [
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{
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||||
"types": "rsa_pub_oem",
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||||
"key_pem": "rsa_pub_oem_dss_key.pem",
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||||
"offset": "0x40",
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||||
"number_id": 0,
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"sha_mode": "SHA512"
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||||
},
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{
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"types": "rsa_pub_oem",
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"key_pem": "P10BMCAspeedSBPubKey_2.pem",
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"offset": "0x240",
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"number_id": 1,
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"sha_mode": "SHA512"
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},
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{
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"types": "rsa_pub_oem",
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"key_pem": "P10BMCAspeedSBPubKey_3.pem",
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"offset": "0x440",
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"number_id": 2,
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"sha_mode": "SHA512"
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}
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],
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"user_data": [
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{
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"types": "dw_hex",
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"file": "emmc_patch.hex",
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"offset": "0x1B80"
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}
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]
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},
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"config_region": {
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"Disable OTP Memory BIST Mode": true,
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"Enable Secure Boot": false,
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"User region ECC enable": true,
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"Secure Region ECC enable": false,
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"Disable low security key": false,
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"Ignore Secure Boot hardware strap": false,
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||||
"Secure Boot Mode": "Mode_2",
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"Disable Uart Message of ROM code": false,
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"Secure crypto RSA length": "RSA4096",
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"Hash mode": "SHA512",
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"Disable patch code": false,
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"Disable Boot from Uart": false,
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"Secure Region size": "0x0",
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"Write Protect: Secure Region": true,
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"Write Protect: User region": true,
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"Write Protect: Configure region": true,
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"Write Protect: OTP strap region": true,
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"Copy Boot Image to Internal SRAM": true,
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"Enable image encryption": false,
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"Enable write Protect of OTP key retire bits": false,
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||||
"Disable Auto Boot from UART or VUART": false,
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"OTP memory lock enable": false,
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"Key Revision": "0x0",
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"Secure boot header offset": "0x0",
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||||
"Boot From UART Port Selection": "UART5",
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"Disable Auto Boot from UART": false,
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"Disable Auto Boot from VUART2 over PCIE": true,
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"Disable Auto Boot from VUART2 over LPC": true,
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"Disable ROM code based programming control": true,
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"Rollback prevention shift bit number": "0x0",
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"Extra Data Write Protection Region Size": "0x0",
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"Erase signature data after secure boot check": false,
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"Erase RSA public key after secure boot check": false,
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"Keys Retire ID": 0,
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"User define data: random number low": "0x0",
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"User define data: random number high": "0x0",
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"Manifest ID": "0x0",
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"Patch code location": "0x6E0",
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"Patch code size": "0x18"
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},
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"otp_strap": {
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"Enable secure boot": { "value": false },
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"Enable boot from eMMC": { "value": true },
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"Boot from debug SPI": { "value": false },
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"Disable ARM CM3": { "value": true },
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"Enable dedicated VGA BIOS ROM": { "value": false },
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"MAC 1 RMII mode": { "value": "RMII/NCSI" },
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"MAC 2 RMII mode": { "value": "RMII/NCSI" },
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"CPU frequency": { "value": "1.2GHz" },
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"HCLK ratio": { "value": "default" },
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"VGA memory size": { "value": "16MB" },
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"CPU/AXI clock ratio": { "value": "2:1" },
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"Disable ARM JTAG debug": { "value": true },
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"VGA class code": { "value": "vga_device" },
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"Disable debug 0": { "value": false },
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"Boot from eMMC speed mode": { "value": "normal" },
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"Enable PCIe EHCI": { "value": false },
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"Disable ARM JTAG trust world debug": { "value": true },
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"Disable dedicated BMC function": { "value": false },
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"Enable dedicate PCIe RC reset": { "value": false },
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"Disable watchdog to reset full chip": { "value": false },
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"Internal bridge speed selection": { "value": "1x" },
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"Disable RVAS function": { "value": false },
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"MAC 3 RMII mode": { "value": "RMII/NCSI" },
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"MAC 4 RMII mode": { "value": "RMII/NCSI" },
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"SuperIO configuration address selection": { "value": "0x2e" },
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"Disable LPC to decode SuperIO": { "value": true },
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"Disable debug 1": { "value": false },
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"Enable ACPI": { "value": false },
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"Select LPC/eSPI": { "value": "LPC" },
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"Enable SAFS": { "value": false },
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"Enable boot from uart5": { "value": false },
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"Enable boot SPI 3B address mode auto-clear": { "value": false },
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"Enable SPI 3B/4B address mode auto detection": { "value": false },
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"Enable boot SPI or eMMC ABR": { "value": true },
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"Boot SPI ABR Mode": { "value": "dual" },
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"Boot SPI flash size": { "value": "0" },
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"Enable host SPI ABR": { "value": false },
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"Enable host SPI ABR mode select pin": { "value": false },
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"Host SPI ABR Mode": { "value": "dual" },
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"Host SPI flash size": { "value": "0" },
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"Enable boot SPI auxiliary control pins": { "value": false },
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"Boot SPI CRTM size": { "value": "0" },
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"Host SPI CRTM size": { "value": "0" },
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"Enable host SPI auxiliary control pins": { "value": false },
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"Enable GPIO Pass Through": { "value": false },
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"Enable Dedicate GPIO Strap Pins": { "value": false }
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}
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}
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@@ -0,0 +1,126 @@
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{
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||||
"name": "p10bmc",
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"version": "A3",
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"data_region": {
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||||
"ecc_region": true,
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||||
"key": [
|
||||
{
|
||||
"types": "rsa_pub_oem",
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"key_pem": "rsa_pub_oem_dss_key.pem",
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"offset": "0x40",
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"number_id": 0,
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"sha_mode": "SHA512"
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},
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{
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"types": "rsa_pub_oem",
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"key_pem": "IPS_P10BMCAspeedSBPubKey_1.pem",
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"offset": "0x240",
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"number_id": 1,
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"sha_mode": "SHA512"
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||||
},
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||||
{
|
||||
"types": "rsa_pub_oem",
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||||
"key_pem": "IPS_P10BMCAspeedSBPubKey_2.pem",
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"offset": "0x440",
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"number_id": 2,
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"sha_mode": "SHA512"
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||||
},
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||||
{
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||||
"types": "rsa_pub_oem",
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||||
"key_pem": "IPS_P10BMCAspeedSBPubKey_3.pem",
|
||||
"offset": "0x640",
|
||||
"number_id": 2,
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"sha_mode": "SHA512"
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||||
}
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||||
]
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||||
},
|
||||
"config_region": {
|
||||
"Disable OTP Memory BIST Mode": true,
|
||||
"Enable Secure Boot": false,
|
||||
"User region ECC enable": true,
|
||||
"Secure Region ECC enable": false,
|
||||
"Disable low security key": false,
|
||||
"Ignore Secure Boot hardware strap": false,
|
||||
"Secure Boot Mode": "Mode_2",
|
||||
"Disable Uart Message of ROM code": false,
|
||||
"Secure crypto RSA length": "RSA4096",
|
||||
"Hash mode": "SHA512",
|
||||
"Disable patch code": true,
|
||||
"Disable Boot from Uart": false,
|
||||
"Secure Region size": "0x0",
|
||||
"Write Protect: Secure Region": true,
|
||||
"Write Protect: User region": true,
|
||||
"Write Protect: Configure region": true,
|
||||
"Write Protect: OTP strap region": true,
|
||||
"Copy Boot Image to Internal SRAM": true,
|
||||
"Enable image encryption": false,
|
||||
"Enable write Protect of OTP key retire bits": false,
|
||||
"Disable Auto Boot from UART or VUART": false,
|
||||
"OTP memory lock enable": false,
|
||||
"Key Revision": "0x0",
|
||||
"Secure boot header offset": "0x0",
|
||||
"Boot From UART Port Selection": "UART5",
|
||||
"Disable Auto Boot from UART": false,
|
||||
"Disable Auto Boot from VUART2 over PCIE": true,
|
||||
"Disable Auto Boot from VUART2 over LPC": true,
|
||||
"Disable ROM code based programming control": true,
|
||||
"Rollback prevention shift bit number": "0x0",
|
||||
"Extra Data Write Protection Region Size": "0x0",
|
||||
"Erase signature data after secure boot check": false,
|
||||
"Erase RSA public key after secure boot check": false,
|
||||
"Keys Retire ID": 0,
|
||||
"User define data: random number low": "0x0",
|
||||
"User define data: random number high": "0x0",
|
||||
"Manifest ID": "0x0",
|
||||
"Patch code location": "0x0",
|
||||
"Patch code size": "0x0"
|
||||
},
|
||||
"otp_strap": {
|
||||
"Enable secure boot": { "value": false },
|
||||
"Enable boot from eMMC": { "value": true },
|
||||
"Boot from debug SPI": { "value": false },
|
||||
"Disable ARM CM3": { "value": true },
|
||||
"Enable dedicated VGA BIOS ROM": { "value": false },
|
||||
"MAC 1 RMII mode": { "value": "RMII/NCSI" },
|
||||
"MAC 2 RMII mode": { "value": "RMII/NCSI" },
|
||||
"CPU frequency": { "value": "1.2GHz" },
|
||||
"HCLK ratio": { "value": "default" },
|
||||
"VGA memory size": { "value": "16MB" },
|
||||
"CPU/AXI clock ratio": { "value": "2:1" },
|
||||
"Disable ARM JTAG debug": { "value": true },
|
||||
"VGA class code": { "value": "vga_device" },
|
||||
"Disable debug 0": { "value": false },
|
||||
"Boot from eMMC speed mode": { "value": "normal" },
|
||||
"Enable PCIe EHCI": { "value": false },
|
||||
"Disable ARM JTAG trust world debug": { "value": true },
|
||||
"Disable dedicated BMC function": { "value": false },
|
||||
"Enable dedicate PCIe RC reset": { "value": false },
|
||||
"Disable watchdog to reset full chip": { "value": false },
|
||||
"Internal bridge speed selection": { "value": "1x" },
|
||||
"Disable RVAS function": { "value": false },
|
||||
"MAC 3 RMII mode": { "value": "RMII/NCSI" },
|
||||
"MAC 4 RMII mode": { "value": "RMII/NCSI" },
|
||||
"SuperIO configuration address selection": { "value": "0x2e" },
|
||||
"Disable LPC to decode SuperIO": { "value": true },
|
||||
"Disable debug 1": { "value": false },
|
||||
"Enable ACPI": { "value": false },
|
||||
"Select LPC/eSPI": { "value": "LPC" },
|
||||
"Enable SAFS": { "value": false },
|
||||
"Enable boot from uart5": { "value": false },
|
||||
"Enable boot SPI 3B address mode auto-clear": { "value": false },
|
||||
"Enable SPI 3B/4B address mode auto detection": { "value": false },
|
||||
"Enable boot SPI or eMMC ABR": { "value": true },
|
||||
"Boot SPI ABR Mode": { "value": "dual" },
|
||||
"Boot SPI flash size": { "value": "0" },
|
||||
"Enable host SPI ABR": { "value": false },
|
||||
"Enable host SPI ABR mode select pin": { "value": false },
|
||||
"Host SPI ABR Mode": { "value": "dual" },
|
||||
"Host SPI flash size": { "value": "0" },
|
||||
"Enable boot SPI auxiliary control pins": { "value": false },
|
||||
"Boot SPI CRTM size": { "value": "0" },
|
||||
"Host SPI CRTM size": { "value": "0" },
|
||||
"Enable host SPI auxiliary control pins": { "value": false },
|
||||
"Enable GPIO Pass Through": { "value": false },
|
||||
"Enable Dedicate GPIO Strap Pins": { "value": false }
|
||||
}
|
||||
}
|
||||
+14
@@ -0,0 +1,14 @@
|
||||
-----BEGIN PUBLIC KEY-----
|
||||
MIICIjANBgkqhkiG9w0BAQEFAAOCAg8AMIICCgKCAgEAoJC0oCngd6B3hfyv+UwZ
|
||||
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||||
xrIf6Mocoh928gr4au6+pzcCAwEAAQ==
|
||||
-----END PUBLIC KEY-----
|
||||
+14
@@ -0,0 +1,14 @@
|
||||
-----BEGIN PUBLIC KEY-----
|
||||
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||||
-----END PUBLIC KEY-----
|
||||
+14
@@ -0,0 +1,14 @@
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||||
-----BEGIN PUBLIC KEY-----
|
||||
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||||
-----END PUBLIC KEY-----
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||||
@@ -0,0 +1,14 @@
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||||
-----BEGIN PUBLIC KEY-----
|
||||
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||||
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|
||||
-----END PUBLIC KEY-----
|
||||
@@ -0,0 +1,14 @@
|
||||
-----BEGIN PUBLIC KEY-----
|
||||
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|
||||
eGNwz+aYm4mWxhqfCuk5MGpovqinD89U6DWxFLPZ9tEH5L1ukT5Xwa5P1qrhWw3B
|
||||
8se2UQarFQzgTrMBME9jcsHtNkiXL5EzSFImxE2/9kF7tgiuJoGBsEMiTABdjHe6
|
||||
0vVD8aHgPxK5JeNQgzOWL4lVMbcVPnwae3C4weniizqRDmSKUWmkza44JGrVwKId
|
||||
B2KR1WWHf81IICqQwCzg9M/Ta2JUWpqz6moer18RhzdRAPV5OEvdoS2QtbbDTVqk
|
||||
EazfTrbO5qPTmwLAqli6rKwBlTGb68hAeWAnC7yQawmv2tgrP7M2KO/0VMXmB9O/
|
||||
oUwRgra3gSfVEm41lo4aZfKRCXJ5H9ZK/tj4m0vE/Epf7vb9CGBYILgXkW77bImp
|
||||
8Q5zyrks9qELi4gx2LPkHyy6WXBwOexFMlnjEnfI0Xmdr1GEwcpAeZ+BsZlN7qeN
|
||||
QnQ71WcCvRXZ307N2chwLi0CAwEAAQ==
|
||||
-----END PUBLIC KEY-----
|
||||
Reference in New Issue
Block a user