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2026-04-23 17:07:55 +08:00
commit b7e39e063b
16725 changed files with 1625565 additions and 0 deletions
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meta-arm/meta-arm-bsp/recipes-kernel/linux/files/corstone1000/0002-Add-external-system-driver.patch
+221
View File
@@ -0,0 +1,221 @@
From 19eabe2a5fb97530820dd2a22fe6bc143a8d693f Mon Sep 17 00:00:00 2001
From: Emekcan <emekcan.aras@arm.com>
Date: Fri, 19 Aug 2022 14:51:08 +0100
Subject: [PATCH 2/6] Add external system driver
Adds external system driver to control it
from user-space. It provides run and reset
functionality at the moment.
Upstream-Status: Pending [Not submitted to upstream yet]
Signed-off-by: Emekcan Aras <emekcan.aras@arm.com>
Signed-off-by: Rui Miguel Silva <rui.silva@linaro.org>
---
drivers/misc/Kconfig | 1 +
drivers/misc/Makefile | 1 +
drivers/misc/arm/Kconfig | 5 ++
drivers/misc/arm/Makefile | 1 +
drivers/misc/arm/extsys_ctrl.c | 151 +++++++++++++++++++++++++++++++++
5 files changed, 159 insertions(+)
create mode 100644 drivers/misc/arm/Kconfig
create mode 100644 drivers/misc/arm/Makefile
create mode 100644 drivers/misc/arm/extsys_ctrl.c
diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig
index 358ad56f6524..fd8654ffdab0 100644
--- a/drivers/misc/Kconfig
+++ b/drivers/misc/Kconfig
@@ -514,4 +514,5 @@ source "drivers/misc/habanalabs/Kconfig"
source "drivers/misc/uacce/Kconfig"
source "drivers/misc/pvpanic/Kconfig"
source "drivers/misc/mchp_pci1xxxx/Kconfig"
+source "drivers/misc/arm/Kconfig"
endmenu
diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile
index ac9b3e757ba1..f7852e4fd63d 100644
--- a/drivers/misc/Makefile
+++ b/drivers/misc/Makefile
@@ -62,3 +62,4 @@ obj-$(CONFIG_HI6421V600_IRQ) += hi6421v600-irq.o
obj-$(CONFIG_OPEN_DICE) += open-dice.o
obj-$(CONFIG_GP_PCI1XXXX) += mchp_pci1xxxx/
obj-$(CONFIG_VCPU_STALL_DETECTOR) += vcpu_stall_detector.o
+obj-y += arm/
diff --git a/drivers/misc/arm/Kconfig b/drivers/misc/arm/Kconfig
new file mode 100644
index 000000000000..9f1eb284e530
--- /dev/null
+++ b/drivers/misc/arm/Kconfig
@@ -0,0 +1,5 @@
+config EXTSYS_CTRL
+ tristate "Arm External System control driver"
+ help
+ Say y here to enable support for external system control
+ driver for the Arm Corstone-700 and Corstone1000 platform
\ No newline at end of file
diff --git a/drivers/misc/arm/Makefile b/drivers/misc/arm/Makefile
new file mode 100644
index 000000000000..1ca3084cf8a0
--- /dev/null
+++ b/drivers/misc/arm/Makefile
@@ -0,0 +1 @@
+obj-$(CONFIG_EXTSYS_CTRL) += extsys_ctrl.o
diff --git a/drivers/misc/arm/extsys_ctrl.c b/drivers/misc/arm/extsys_ctrl.c
new file mode 100644
index 000000000000..7929070ff43d
--- /dev/null
+++ b/drivers/misc/arm/extsys_ctrl.c
@@ -0,0 +1,151 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Arm Corstone700 and Corstone1000 external system reset control driver
+ *
+ * Copyright (C) 2019 Arm Ltd.
+ *
+ */
+
+#include <linux/fs.h>
+#include <linux/clk.h>
+#include <linux/err.h>
+#include <linux/interrupt.h>
+#include <linux/io.h>
+#include <linux/kernel.h>
+#include <linux/mod_devicetable.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/miscdevice.h>
+#include <linux/init.h>
+
+#define EXTSYS_DRV_NAME "extsys_ctrl"
+#define EXTSYS_MAX_DEVS 4
+
+#define EXTSYS_RST_SIZE U(0x8)
+#define EXTSYS_RST_CTRL_OFF U(0x0)
+#define EXTSYS_RST_ST_OFF U(0x4)
+
+/* External system reset control indexes */
+#define EXTSYS_CPU_WAIT (0x0)
+#define EXTSYS_RST_REQ (0x1)
+
+/* External system reset status masks */
+#define EXTSYS_RST_ST_ACK_OFF U(0x1)
+
+/* No Reset Requested */
+#define EXTSYS_RST_ST_ACK_NRR (0x0 << EXTSYS_RST_ST_ACK_OFF)
+
+/* Reset Request Complete */
+#define EXTSYS_RST_ST_ACK_RRC (0x2 << EXTSYS_RST_ST_ACK_OFF)
+
+/* Reset Request Unable to Complete */
+#define EXTSYS_RST_ST_ACK_RRUC (0x3 << EXTSYS_RST_ST_ACK_OFF)
+
+/* IOCTL commands */
+#define EXTSYS_CPU_WAIT_DISABLE 0x0
+#define EXTSYS_RESET_REQ_ENABLE 0x1
+
+struct extsys_ctrl {
+ struct miscdevice miscdev;
+ void __iomem *reset_reg;
+ void __iomem *set_reg;
+};
+
+#define CLEAR_BIT(addr, index) writel(readl(addr) & ~(1UL << index), addr)
+#define SET_BIT(addr, index) writel(readl(addr) | (1UL << index), addr)
+
+static long extsys_ctrl_ioctl(struct file *f, unsigned int cmd,
+ unsigned long arg)
+{
+ struct extsys_ctrl *extsys;
+
+ extsys = container_of(f->private_data, struct extsys_ctrl, miscdev);
+
+ switch (cmd) {
+ case EXTSYS_CPU_WAIT_DISABLE:
+ CLEAR_BIT(extsys->reset_reg, EXTSYS_CPU_WAIT);
+ break;
+ case EXTSYS_RESET_REQ_ENABLE:
+ SET_BIT(extsys->reset_reg, EXTSYS_RST_REQ);
+ break;
+ default:
+ break;
+ }
+
+ return 0;
+}
+
+static const struct file_operations extsys_ctrl_fops = {
+ .owner = THIS_MODULE,
+ .unlocked_ioctl = extsys_ctrl_ioctl,
+};
+
+static int extsys_ctrl_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct extsys_ctrl *extsys;
+ struct resource *res;
+ void __iomem *reset_reg;
+ void __iomem *set_reg;
+ int ret;
+
+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "rstreg");
+ reset_reg = devm_ioremap_resource(dev, res);
+ if (IS_ERR(reset_reg))
+ return PTR_ERR(reset_reg);
+
+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "streg");
+ set_reg = devm_ioremap_resource(dev, res);
+ if (IS_ERR(set_reg))
+ return PTR_ERR(set_reg);
+
+ extsys = devm_kzalloc(dev, sizeof(*extsys), GFP_KERNEL);
+ if (!extsys)
+ return -ENOMEM;
+
+ extsys->reset_reg = reset_reg;
+ extsys->set_reg = set_reg;
+
+ extsys->miscdev.minor = MISC_DYNAMIC_MINOR;
+ extsys->miscdev.name = EXTSYS_DRV_NAME;
+ extsys->miscdev.fops = &extsys_ctrl_fops;
+ extsys->miscdev.parent = dev;
+
+ ret = misc_register(&extsys->miscdev);
+ if (ret)
+ return ret;
+
+ dev_info(dev, "external system controller ready\n");
+
+ return 0;
+}
+
+static int extsys_ctrl_remove(struct platform_device *pdev)
+{
+ struct extsys_ctrl *extsys = dev_get_drvdata(&pdev->dev);
+
+ misc_deregister(&extsys->miscdev);
+
+ return 0;
+}
+
+static const struct of_device_id extsys_ctrl_match[] = {
+ { .compatible = "arm,extsys_ctrl" },
+ { },
+};
+MODULE_DEVICE_TABLE(of, extsys_ctrl_match);
+
+static struct platform_driver extsys_ctrl_driver = {
+ .driver = {
+ .name = EXTSYS_DRV_NAME,
+ .of_match_table = extsys_ctrl_match,
+ },
+ .probe = extsys_ctrl_probe,
+ .remove = extsys_ctrl_remove,
+};
+module_platform_driver(extsys_ctrl_driver);
+
+MODULE_LICENSE("GPL v2");
+MODULE_DESCRIPTION("Arm External System Control Driver");
+MODULE_AUTHOR("Morten Borup Petersen");
+MODULE_AUTHOR("Rui Miguel Silva <rui.silva@arm.com>");
--
2.39.0
meta-arm/meta-arm-bsp/recipes-kernel/linux/files/corstone1000/0003-Add-rpmsg-driver-for-corstone1000.patch
+221
View File
@@ -0,0 +1,221 @@
From 9fb971c23d423f593620ed82fb69a7e2cd35986a Mon Sep 17 00:00:00 2001
From: Emekcan <emekcan.aras@arm.com>
Date: Wed, 17 Aug 2022 14:21:42 +0100
Subject: [PATCH 3/6] Add rpmsg driver for corstone1000
Adds rpmsg driver to communicate with external
system in corstone1000 platform.
Upstream-Status: Pending
Signed-off-by: Emekcan Aras <emekcan.aras@arm.com>
Signed-off-by: Rui Miguel Silva <rui.silva@linaro.org>
---
drivers/rpmsg/Kconfig | 10 ++
drivers/rpmsg/Makefile | 1 +
drivers/rpmsg/rpmsg_arm_mailbox.c | 164 ++++++++++++++++++++++++++++++
3 files changed, 175 insertions(+)
create mode 100644 drivers/rpmsg/rpmsg_arm_mailbox.c
diff --git a/drivers/rpmsg/Kconfig b/drivers/rpmsg/Kconfig
index d3795860f5c0..fc6916d7b523 100644
--- a/drivers/rpmsg/Kconfig
+++ b/drivers/rpmsg/Kconfig
@@ -81,4 +81,14 @@ config RPMSG_VIRTIO
select RPMSG_NS
select VIRTIO
+config RPMSG_ARM
+ tristate "ARM RPMSG driver"
+ select RPMSG
+ depends on HAS_IOMEM
+ depends on MAILBOX
+ help
+ Say y here to enable support for rpmsg lient driver which is built
+ around mailbox client using Arm MHUv2.1 as physical medium.This
+ driver enables communication which remote processor using MHU.
+
endmenu
diff --git a/drivers/rpmsg/Makefile b/drivers/rpmsg/Makefile
index 58e3b382e316..6bdcc69688b2 100644
--- a/drivers/rpmsg/Makefile
+++ b/drivers/rpmsg/Makefile
@@ -1,5 +1,6 @@
# SPDX-License-Identifier: GPL-2.0
obj-$(CONFIG_RPMSG) += rpmsg_core.o
+obj-$(CONFIG_RPMSG_ARM) += rpmsg_arm_mailbox.o
obj-$(CONFIG_RPMSG_CHAR) += rpmsg_char.o
obj-$(CONFIG_RPMSG_CTRL) += rpmsg_ctrl.o
obj-$(CONFIG_RPMSG_NS) += rpmsg_ns.o
diff --git a/drivers/rpmsg/rpmsg_arm_mailbox.c b/drivers/rpmsg/rpmsg_arm_mailbox.c
new file mode 100644
index 000000000000..4a80102669f6
--- /dev/null
+++ b/drivers/rpmsg/rpmsg_arm_mailbox.c
@@ -0,0 +1,164 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * rpmsg client driver using mailbox client interface
+ *
+ * Copyright (C) 2019 ARM Ltd.
+ *
+ */
+
+#include <linux/bitmap.h>
+#include <linux/export.h>
+#include <linux/io.h>
+#include <linux/kernel.h>
+#include <linux/ktime.h>
+#include <linux/mailbox_client.h>
+#include <linux/module.h>
+#include <linux/of_address.h>
+#include <linux/of_device.h>
+#include <linux/processor.h>
+#include <linux/semaphore.h>
+#include <linux/slab.h>
+#include <linux/rpmsg.h>
+#include "rpmsg_internal.h"
+#include <linux/mailbox/arm_mhuv2_message.h>
+
+#define RPMSG_NAME "arm_rpmsg"
+#define RPMSG_ADDR_ANY 0xFFFFFFFF
+
+struct arm_channel {
+ struct rpmsg_endpoint ept;
+ struct mbox_client cl;
+ struct mbox_chan *mbox;
+};
+
+#define arm_channel_from_rpmsg(_ept) container_of(_ept, struct arm_channel, ept)
+#define arm_channel_from_mbox(_ept) container_of(_ept, struct arm_channel, cl)
+
+
+static void arm_msg_rx_handler(struct mbox_client *cl, void *mssg)
+{
+ struct arm_mhuv2_mbox_msg *msg = mssg;
+ struct arm_channel* channel = arm_channel_from_mbox(cl);
+ int err = channel->ept.cb(channel->ept.rpdev, msg->data, 4, channel->ept.priv, RPMSG_ADDR_ANY);
+ if(err) {
+ printk("ARM Mailbox: Endpoint callback failed with error: %d", err);
+ }
+}
+
+
+static void arm_destroy_ept(struct rpmsg_endpoint *ept)
+{
+ struct arm_channel *channel = arm_channel_from_rpmsg(ept);
+ mbox_free_channel(channel->mbox);
+ kfree(channel);
+}
+
+static int arm_send(struct rpmsg_endpoint *ept, void *data, int len)
+{
+ struct arm_channel *channel = arm_channel_from_rpmsg(ept);
+
+ mbox_send_message(channel->mbox, data);
+ return 0;
+}
+
+static int arm_sendto(struct rpmsg_endpoint *ept, void *data, int len, u32 dest)
+{
+ struct arm_mhuv2_mbox_msg msg;
+ struct arm_channel *channel = arm_channel_from_rpmsg(ept);
+ msg.data = data;
+ msg.len = len;
+ mbox_send_message(channel->mbox, &msg);
+ return 0;
+}
+
+
+static const struct rpmsg_endpoint_ops arm_endpoint_ops = {
+ .destroy_ept = arm_destroy_ept,
+ .send = arm_send,
+ .sendto = arm_sendto,
+};
+
+
+static struct rpmsg_endpoint *arm_create_ept(struct rpmsg_device *rpdev,
+ rpmsg_rx_cb_t cb, void *priv, struct rpmsg_channel_info chinfo)
+{
+ struct arm_channel *channel;
+
+ channel = kzalloc(sizeof(*channel), GFP_KERNEL);
+
+ // Initialize rpmsg endpoint
+ kref_init(&channel->ept.refcount);
+ channel->ept.rpdev = rpdev;
+ channel->ept.cb = cb;
+ channel->ept.priv = priv;
+ channel->ept.ops = &arm_endpoint_ops;
+
+ // Initialize mailbox client
+ channel->cl.dev = rpdev->dev.parent;
+ channel->cl.rx_callback = arm_msg_rx_handler;
+ channel->cl.tx_done = NULL; /* operate in blocking mode */
+ channel->cl.tx_block = true;
+ channel->cl.tx_tout = 500; /* by half a second */
+ channel->cl.knows_txdone = false; /* depending upon protocol */
+
+ channel->mbox = mbox_request_channel_byname(&channel->cl, chinfo.name);
+ if (IS_ERR_OR_NULL(channel->mbox)) {
+ printk("RPMsg ARM: Cannot get channel by name: '%s'\n", chinfo.name);
+ return -1;
+ }
+
+ return &channel->ept;
+}
+
+static const struct rpmsg_device_ops arm_device_ops = {
+ .create_ept = arm_create_ept,
+};
+
+
+static void arm_release_device(struct device *dev)
+{
+ struct rpmsg_device *rpdev = to_rpmsg_device(dev);
+
+ kfree(rpdev);
+}
+
+
+static int client_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct rpmsg_device *rpdev;
+
+ rpdev = kzalloc(sizeof(*rpdev), GFP_KERNEL);
+ if (!rpdev)
+ return -ENOMEM;
+
+ /* Assign callbacks for rpmsg_device */
+ rpdev->ops = &arm_device_ops;
+
+ /* Assign public information to the rpmsg_device */
+ memcpy(rpdev->id.name, RPMSG_NAME, strlen(RPMSG_NAME));
+
+ rpdev->dev.parent = dev;
+ rpdev->dev.release = arm_release_device;
+
+ return rpmsg_chrdev_register_device(rpdev);
+}
+
+static const struct of_device_id client_of_match[] = {
+ { .compatible = "arm,client", .data = NULL },
+ { /* Sentinel */ },
+};
+
+static struct platform_driver client_driver = {
+ .driver = {
+ .name = "arm-mhu-client",
+ .of_match_table = client_of_match,
+ },
+ .probe = client_probe,
+};
+
+module_platform_driver(client_driver);
+
+MODULE_LICENSE("GPL v2");
+MODULE_DESCRIPTION("ARM RPMSG Driver");
+MODULE_AUTHOR("Tushar Khandelwal <tushar.khandelwal@arm.com>");
--
2.39.0
meta-arm/meta-arm-bsp/recipes-kernel/linux/files/corstone1000/0004-rpmsg-arm-fix-return-value.patch
+33
View File
@@ -0,0 +1,33 @@
From ce77351c8ae6b04070135fdaedaad337bb0b4ef5 Mon Sep 17 00:00:00 2001
From: Rui Miguel Silva <rui.silva@linaro.org>
Date: Tue, 27 Sep 2022 10:05:27 +0100
Subject: [PATCH 4/6] rpmsg: arm: fix return value
The creation of and endpoint returns a pointer, fix the return
value to the right type.
Upstream-Status: Pending
Signed-off-by: Rui Miguel Silva <rui.silva@linaro.org>
---
drivers/rpmsg/rpmsg_arm_mailbox.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers/rpmsg/rpmsg_arm_mailbox.c b/drivers/rpmsg/rpmsg_arm_mailbox.c
index 4a80102669f6..5c0dcc8e353d 100644
--- a/drivers/rpmsg/rpmsg_arm_mailbox.c
+++ b/drivers/rpmsg/rpmsg_arm_mailbox.c
@@ -103,8 +103,9 @@ static struct rpmsg_endpoint *arm_create_ept(struct rpmsg_device *rpdev,
channel->mbox = mbox_request_channel_byname(&channel->cl, chinfo.name);
if (IS_ERR_OR_NULL(channel->mbox)) {
- printk("RPMsg ARM: Cannot get channel by name: '%s'\n", chinfo.name);
- return -1;
+ printk("RPMsg ARM: Cannot get channel by name: %s\n",
+ chinfo.name);
+ return ERR_PTR(-ENOENT);
}
return &channel->ept;
--
2.39.0
meta-arm/meta-arm-bsp/recipes-kernel/linux/files/corstone1000/0005-rpmsg-arm-update-chrdev-to-ctrldev-registration.patch
+31
View File
@@ -0,0 +1,31 @@
From 590bf152e18b3cf7166c7accfc32ed3b2d07bf09 Mon Sep 17 00:00:00 2001
From: Rui Miguel Silva <rui.silva@linaro.org>
Date: Tue, 27 Sep 2022 10:07:21 +0100
Subject: [PATCH 5/6] rpmsg: arm: update chrdev to ctrldev registration
Since "rpmsg: Update rpmsg_chrdev_register_device function",
there was a replacement of the chrdev driver to ctrldev
driver. Fix the registration.
Upstream-Status: Pending
Signed-off-by: Rui Miguel Silva <rui.silva@linaro.org>
---
drivers/rpmsg/rpmsg_arm_mailbox.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/rpmsg/rpmsg_arm_mailbox.c b/drivers/rpmsg/rpmsg_arm_mailbox.c
index 5c0dcc8e353d..90bc8df90885 100644
--- a/drivers/rpmsg/rpmsg_arm_mailbox.c
+++ b/drivers/rpmsg/rpmsg_arm_mailbox.c
@@ -142,7 +142,7 @@ static int client_probe(struct platform_device *pdev)
rpdev->dev.parent = dev;
rpdev->dev.release = arm_release_device;
- return rpmsg_chrdev_register_device(rpdev);
+ return rpmsg_ctrldev_register_device(rpdev);
}
static const struct of_device_id client_of_match[] = {
--
2.39.0
meta-arm/meta-arm-bsp/recipes-kernel/linux/files/corstone1000/0006-Adds-workaround-for-cs1k-specific-bug.patch
+40
View File
@@ -0,0 +1,40 @@
From 00851c43f4d00e7451550660ab652e9ac9128e02 Mon Sep 17 00:00:00 2001
From: Emekcan <emekcan.aras@arm.com>
Date: Thu, 13 Oct 2022 20:53:42 +0100
Subject: [PATCH 6/6] Adds workaround for cs1k specific bug
Adds a temporary workaround to solve a possible
race-conditioning issue in the tee driver
for corstone1000.
Upstream-Status: Inappropriate
Signed-off-by: Emekcan Aras <emekcan.aras@arm.com>
Signed-off-by: Rui Miguel Silva <rui.silva@linaro.org>
---
drivers/firmware/arm_ffa/driver.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/firmware/arm_ffa/driver.c b/drivers/firmware/arm_ffa/driver.c
index d5e86ef40b89..cbb944f63321 100644
--- a/drivers/firmware/arm_ffa/driver.c
+++ b/drivers/firmware/arm_ffa/driver.c
@@ -32,6 +32,7 @@
#include <linux/scatterlist.h>
#include <linux/slab.h>
#include <linux/uuid.h>
+#include <linux/delay.h>
#include "common.h"
@@ -362,7 +363,7 @@ static int ffa_msg_send_direct_req(u16 src_id, u16 dst_id, bool mode_32bit,
{
u32 req_id, resp_id, src_dst_ids = PACK_TARGET_INFO(src_id, dst_id);
ffa_value_t ret;
-
+ msleep(1);
if (mode_32bit) {
req_id = FFA_MSG_SEND_DIRECT_REQ;
resp_id = FFA_MSG_SEND_DIRECT_RESP;
--
2.39.0
meta-arm/meta-arm-bsp/recipes-kernel/linux/files/corstone1000/corstone1000_kernel_debug.cfg
+3
View File
@@ -0,0 +1,3 @@
CONFIG_DEBUG_INFO=y
CONFIG_DEBUG_KERNEL=y
CONFIG_DEBUG_INFO_DWARF4=y
meta-arm/meta-arm-bsp/recipes-kernel/linux/files/corstone1000/defconfig
+100
View File
@@ -0,0 +1,100 @@
CONFIG_LOCALVERSION="-yocto-standard"
# CONFIG_LOCALVERSION_AUTO is not set
CONFIG_HIGH_RES_TIMERS=y
CONFIG_PREEMPT=y
CONFIG_LOG_BUF_SHIFT=13
CONFIG_LOG_CPU_MAX_BUF_SHIFT=13
CONFIG_RELAY=y
CONFIG_BOOT_CONFIG=y
CONFIG_ARCH_VEXPRESS=y
CONFIG_CMDLINE="console=ttyAMA0 loglevel=9"
CONFIG_EFI=y
# CONFIG_SUSPEND is not set
CONFIG_EFI_BOOTLOADER_CONTROL=y
CONFIG_EFI_CAPSULE_LOADER=y
CONFIG_EFI_TEST=y
CONFIG_RESET_ATTACK_MITIGATION=y
# CONFIG_STACKPROTECTOR is not set
CONFIG_MODULES=y
# CONFIG_BLK_DEV_BSG is not set
# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
CONFIG_NET=y
CONFIG_PACKET=y
CONFIG_UNIX=y
CONFIG_INET=y
CONFIG_IP_PNP=y
CONFIG_IP_PNP_DHCP=y
CONFIG_IP_PNP_BOOTP=y
CONFIG_SYN_COOKIES=y
CONFIG_NET_SCHED=y
CONFIG_DEVTMPFS=y
CONFIG_SCSI=y
CONFIG_BLK_DEV_SD=y
CONFIG_NETDEVICES=y
# CONFIG_NET_VENDOR_ALACRITECH is not set
# CONFIG_NET_VENDOR_AMAZON is not set
# CONFIG_NET_VENDOR_AMD is not set
# CONFIG_NET_VENDOR_AQUANTIA is not set
# CONFIG_NET_VENDOR_ARC is not set
# CONFIG_NET_VENDOR_BROADCOM is not set
# CONFIG_NET_VENDOR_CADENCE is not set
# CONFIG_NET_VENDOR_CAVIUM is not set
# CONFIG_NET_VENDOR_CORTINA is not set
# CONFIG_NET_VENDOR_EZCHIP is not set
# CONFIG_NET_VENDOR_GOOGLE is not set
# CONFIG_NET_VENDOR_HISILICON is not set
# CONFIG_NET_VENDOR_HUAWEI is not set
# CONFIG_NET_VENDOR_INTEL is not set
# CONFIG_NET_VENDOR_MARVELL is not set
# CONFIG_NET_VENDOR_MICREL is not set
# CONFIG_NET_VENDOR_MICROCHIP is not set
# CONFIG_NET_VENDOR_MICROSEMI is not set
# CONFIG_NET_VENDOR_NATSEMI is not set
# CONFIG_NET_VENDOR_NETRONOME is not set
# CONFIG_NET_VENDOR_NI is not set
# CONFIG_NET_VENDOR_PENSANDO is not set
# CONFIG_NET_VENDOR_QUALCOMM is not set
# CONFIG_NET_VENDOR_RENESAS is not set
# CONFIG_NET_VENDOR_ROCKER is not set
# CONFIG_NET_VENDOR_SAMSUNG is not set
# CONFIG_NET_VENDOR_SEEQ is not set
# CONFIG_NET_VENDOR_SOLARFLARE is not set
CONFIG_SMC91X=y
CONFIG_SMSC911X=y
# CONFIG_NET_VENDOR_SOCIONEXT is not set
# CONFIG_NET_VENDOR_STMICRO is not set
# CONFIG_NET_VENDOR_SYNOPSYS is not set
# CONFIG_NET_VENDOR_VIA is not set
# CONFIG_NET_VENDOR_WIZNET is not set
# CONFIG_NET_VENDOR_XILINX is not set
# CONFIG_SERIO_SERPORT is not set
CONFIG_SERIAL_AMBA_PL011=y
CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_USB_UAS=y
CONFIG_USB_ISP1760=y
CONFIG_RTC_CLASS=y
CONFIG_RTC_DRV_PL031=y
CONFIG_TEE=y
CONFIG_OPTEE=y
CONFIG_VFAT_FS=y
CONFIG_TMPFS=y
CONFIG_CONFIGFS_FS=y
CONFIG_NLS_CODEPAGE_437=y
CONFIG_NLS_CODEPAGE_860=y
CONFIG_NLS_ISO8859_1=y
CONFIG_NLS_ISO8859_15=y
CONFIG_NLS_UTF8=y
CONFIG_LIBCRC32C=y
# CONFIG_SECTION_MISMATCH_WARN_ONLY is not set
CONFIG_DEBUG_FS=y
CONFIG_PANIC_TIMEOUT=5
CONFIG_STACKTRACE=y
CONFIG_EXTSYS_CTRL=y
CONFIG_MAILBOX=y
CONFIG_ARM_MHU_V2=y
CONFIG_RPMSG=y
CONFIG_RPMSG_CHAR=y
CONFIG_RPMSG_ARM=y
CONFIG_RPMSG_CTRL=y
meta-arm/meta-arm-bsp/recipes-kernel/linux/files/fvp-base/0001-arm64-dts-fvp-Enable-virtio-rng-support.patch
+29
View File
@@ -0,0 +1,29 @@
From b443c8efd563dc372c60e7ad9f52aeddf7c13706 Mon Sep 17 00:00:00 2001
From: Anton Antonov <Anton.Antonov@arm.com>
Date: Mon, 7 Nov 2022 11:37:51 +0000
Subject: [PATCH] arm64: dts: fvp: Enable virtio-rng support
The virtio-rng is available from FVP_Base_RevC-2xAEMvA version 11.17.
Enable it since Yocto includes a recipe for a newer FVP version.
Upstream-Status: Inappropriate [Yocto specific]
Signed-off-by: Anton Antonov <Anton.Antonov@arm.com>
---
arch/arm64/boot/dts/arm/rtsm_ve-motherboard-rs2.dtsi | 1 -
1 file changed, 1 deletion(-)
diff --git a/arch/arm64/boot/dts/arm/rtsm_ve-motherboard-rs2.dtsi b/arch/arm64/boot/dts/arm/rtsm_ve-motherboard-rs2.dtsi
index ec2d5280a30b..acafdcbf1063 100644
--- a/arch/arm64/boot/dts/arm/rtsm_ve-motherboard-rs2.dtsi
+++ b/arch/arm64/boot/dts/arm/rtsm_ve-motherboard-rs2.dtsi
@@ -26,7 +26,6 @@ virtio@200000 {
compatible = "virtio,mmio";
reg = <0x200000 0x200>;
interrupts = <46>;
- status = "disabled";
};
};
};
--
2.25.1
meta-arm/meta-arm-bsp/recipes-kernel/linux/files/fvp-baser-aemv8r64/fvp-baser-aemv8r64.dts
+212
View File
@@ -0,0 +1,212 @@
/dts-v1/;
/ {
#address-cells = <0x2>;
#size-cells = <0x2>;
interrupt-parent = <0x1>;
model = "Generated";
compatible = "arm,base";
memory@0 {
#address-cells = <0x2>;
#size-cells = <0x2>;
device_type = "memory";
reg = <0x0 0x0 0x0 0x80000000>,
<0x00000008 0x80000000 0x0 0x80000000>;
};
cpus {
#address-cells = <0x2>;
#size-cells = <0x0>;
cpu-map {
cluster0 {
core0 { thread0 { cpu = <&CPU_0>; }; };
core1 { thread0 { cpu = <&CPU_1>; }; };
core2 { thread0 { cpu = <&CPU_2>; }; };
core3 { thread0 { cpu = <&CPU_3>; }; };
};
};
CPU_0: cpu@0 {
device_type = "cpu";
compatible = "arm,armv8";
reg = <0x0 0x0>;
enable-method = "spin-table";
cpu-release-addr = <0x0 0x7f800>;
};
CPU_1: cpu@1 {
device_type = "cpu";
compatible = "arm,armv8";
reg = <0x0 0x1>;
enable-method = "spin-table";
cpu-release-addr = <0x0 0x7f808>;
};
CPU_2: cpu@2 {
device_type = "cpu";
compatible = "arm,armv8";
reg = <0x0 0x2>;
enable-method = "spin-table";
cpu-release-addr = <0x0 0x7f810>;
};
CPU_3: cpu@3 {
device_type = "cpu";
compatible = "arm,armv8";
reg = <0x0 0x3>;
enable-method = "spin-table";
cpu-release-addr = <0x0 0x7f818>;
};
};
interrupt-controller@af000000 {
compatible = "arm,gic-v3";
#interrupt-cells = <0x3>;
#address-cells = <0x2>;
#size-cells = <0x2>;
ranges;
interrupt-controller;
#redistributor-regions = <0x1>;
reg = <0x0 0xaf000000 0x0 0x10000>, // GICD
<0x0 0xaf100000 0x0 0x100000>, // GICR
<0x0 0xac000000 0x0 0x2000>, // GICC
<0x0 0xac010000 0x0 0x2000>, // GICH
<0x0 0xac02f000 0x0 0x2000>; // GICV
interrupts = <0x1 9 0x4>;
linux,phandle = <0x1>;
phandle = <0x1>;
its: msi-controller@2f020000 {
#msi-cells = <1>;
compatible = "arm,gic-v3-its";
reg = <0x0 0xaf020000 0x0 0x20000>; // GITS
msi-controller;
};
};
refclk100mhz: refclk100mhz {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <100000000>;
clock-output-names = "apb_pclk";
};
refclk24mhz: refclk24mhz {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <24000000>;
clock-output-names = "refclk24mhz";
};
refclk1hz: refclk1hz {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <1>;
clock-output-names = "refclk1hz";
};
uart@9c090000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x0 0x9c090000 0x0 0x1000>;
interrupts = <0x0 5 0x4>;
clocks = <&refclk24mhz>, <&refclk100mhz>;
clock-names = "uartclk", "apb_pclk";
};
uart@9c0a0000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x0 0x9c0a0000 0x0 0x1000>;
interrupts = <0x0 6 0x4>;
clocks = <&refclk24mhz>, <&refclk100mhz>;
clock-names = "uartclk", "apb_pclk";
};
uart@9c0b0000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x0 0x9c0b0000 0x0 0x1000>;
interrupts = <0x0 7 0x4>;
clocks = <&refclk24mhz>, <&refclk100mhz>;
clock-names = "uartclk", "apb_pclk";
};
uart@9c0c0000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x0 0x9c0c0000 0x0 0x1000>;
interrupts = <0x0 8 0x4>;
clocks = <&refclk24mhz>, <&refclk100mhz>;
clock-names = "uartclk", "apb_pclk";
};
wdt@9c0f0000 {
compatible = "arm,sp805", "arm,primecell";
reg = <0x0 0x9c0f0000 0x0 0x1000>;
interrupts = <0x0 0 0x4>;
clocks = <&refclk24mhz>, <&refclk100mhz>;
clock-names = "wdog_clk", "apb_pclk";
};
rtc@9c170000 {
compatible = "arm,pl031", "arm,primecell";
reg = <0x0 0x9c170000 0x0 0x1000>;
interrupts = <0x0 4 0x4>;
clocks = <&refclk1hz>;
clock-names = "apb_pclk";
};
virtio-block@9c130000 {
compatible = "virtio,mmio";
reg = <0 0x9c130000 0 0x200>;
interrupts = <0x0 42 0x4>;
};
virtio-p9@9c140000{
compatible = "virtio,mmio";
reg = <0x0 0x9c140000 0x0 0x1000>;
interrupts = <0x0 43 0x4>;
};
virtio-net@9c150000 {
compatible = "virtio,mmio";
reg = <0 0x9c150000 0 0x200>;
interrupts = <0x0 44 0x4>;
};
virtio-rng@9c200000 {
compatible = "virtio,mmio";
reg = <0 0x9c200000 0 0x200>;
interrupts = <0x0 46 0x4>;
};
timer {
compatible = "arm,armv8-timer";
interrupts = <0x1 13 0xff08>,
<0x1 14 0xff08>,
<0x1 11 0xff08>,
<0x1 4 0xff08>;
clock-frequency = <100000000>;
};
aliases {
serial0 = "/uart@9c090000";
serial1 = "/uart@9c0a0000";
serial2 = "/uart@9c0b0000";
serial3 = "/uart@9c0c0000";
};
pmu {
compatible = "arm,armv8-pmuv3";
interrupts = <0 60 4>,
<0 61 4>,
<0 62 4>,
<0 63 4>;
};
chosen {
bootargs = "earlycon console=ttyAMA0 loglevel=8 rootfstype=ext4 root=/dev/vda1 rw";
stdout-path = "serial0";
};
};
meta-arm/meta-arm-bsp/recipes-kernel/linux/files/juno/0001-arm64-dts-Update-cache-properties-for-Arm-Ltd-platfo.patch
+138
View File
@@ -0,0 +1,138 @@
From dc250cab31c6611cc7fa76bc8b2027dbd56dd65d Mon Sep 17 00:00:00 2001
From: Pierre Gondois <pierre.gondois@arm.com>
Date: Mon, 7 Nov 2022 16:56:58 +0100
Subject: [PATCH] arm64: dts: Update cache properties for Arm Ltd platforms
The DeviceTree Specification v0.3 specifies that the cache node
"compatible" and "cache-level" properties are required.
Cf. s3.8 Multi-level and Shared Cache Nodes
The 'cache-unified' property should be present if one of the properties
for unified cache is present ('cache-size', ...).
Update the relevant device trees nodes accordingly.
Signed-off-by: Pierre Gondois <pierre.gondois@arm.com>
Link: https://lore.kernel.org/r/20221107155825.1644604-6-pierre.gondois@arm.com
Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
Signed-off-by: Jon Mason <jon.mason@arm.com>
Upstream-Status: Backport
---
arch/arm64/boot/dts/arm/corstone1000.dtsi | 1 +
arch/arm64/boot/dts/arm/foundation-v8.dtsi | 1 +
arch/arm64/boot/dts/arm/juno-r1.dts | 2 ++
arch/arm64/boot/dts/arm/juno-r2.dts | 2 ++
arch/arm64/boot/dts/arm/juno.dts | 2 ++
arch/arm64/boot/dts/arm/rtsm_ve-aemv8a.dts | 1 +
arch/arm64/boot/dts/arm/vexpress-v2f-1xv7-ca53x2.dts | 1 +
7 files changed, 10 insertions(+)
diff --git a/arch/arm64/boot/dts/arm/corstone1000.dtsi b/arch/arm64/boot/dts/arm/corstone1000.dtsi
index 4e46826f883a..21f1f952e985 100644
--- a/arch/arm64/boot/dts/arm/corstone1000.dtsi
+++ b/arch/arm64/boot/dts/arm/corstone1000.dtsi
@@ -53,6 +53,7 @@ gic: interrupt-controller@1c000000 {
L2_0: l2-cache0 {
compatible = "cache";
+ cache-unified;
cache-level = <2>;
cache-size = <0x80000>;
cache-line-size = <64>;
diff --git a/arch/arm64/boot/dts/arm/foundation-v8.dtsi b/arch/arm64/boot/dts/arm/foundation-v8.dtsi
index 83e3e7e3984f..c8bd23b1a7ba 100644
--- a/arch/arm64/boot/dts/arm/foundation-v8.dtsi
+++ b/arch/arm64/boot/dts/arm/foundation-v8.dtsi
@@ -58,6 +58,7 @@ cpu3: cpu@3 {
L2_0: l2-cache0 {
compatible = "cache";
+ cache-level = <2>;
};
};
diff --git a/arch/arm64/boot/dts/arm/juno-r1.dts b/arch/arm64/boot/dts/arm/juno-r1.dts
index 6451c62146fd..1d90eeebb37d 100644
--- a/arch/arm64/boot/dts/arm/juno-r1.dts
+++ b/arch/arm64/boot/dts/arm/juno-r1.dts
@@ -189,6 +189,7 @@ A53_3: cpu@103 {
A57_L2: l2-cache0 {
compatible = "cache";
+ cache-unified;
cache-size = <0x200000>;
cache-line-size = <64>;
cache-sets = <2048>;
@@ -197,6 +198,7 @@ A57_L2: l2-cache0 {
A53_L2: l2-cache1 {
compatible = "cache";
+ cache-unified;
cache-size = <0x100000>;
cache-line-size = <64>;
cache-sets = <1024>;
diff --git a/arch/arm64/boot/dts/arm/juno-r2.dts b/arch/arm64/boot/dts/arm/juno-r2.dts
index 438cd1ff4bd0..d2ada69b0a43 100644
--- a/arch/arm64/boot/dts/arm/juno-r2.dts
+++ b/arch/arm64/boot/dts/arm/juno-r2.dts
@@ -195,6 +195,7 @@ A53_3: cpu@103 {
A72_L2: l2-cache0 {
compatible = "cache";
+ cache-unified;
cache-size = <0x200000>;
cache-line-size = <64>;
cache-sets = <2048>;
@@ -203,6 +204,7 @@ A72_L2: l2-cache0 {
A53_L2: l2-cache1 {
compatible = "cache";
+ cache-unified;
cache-size = <0x100000>;
cache-line-size = <64>;
cache-sets = <1024>;
diff --git a/arch/arm64/boot/dts/arm/juno.dts b/arch/arm64/boot/dts/arm/juno.dts
index cf4a58211399..5e48a01a5b9f 100644
--- a/arch/arm64/boot/dts/arm/juno.dts
+++ b/arch/arm64/boot/dts/arm/juno.dts
@@ -194,6 +194,7 @@ A53_3: cpu@103 {
A57_L2: l2-cache0 {
compatible = "cache";
+ cache-unified;
cache-size = <0x200000>;
cache-line-size = <64>;
cache-sets = <2048>;
@@ -202,6 +203,7 @@ A57_L2: l2-cache0 {
A53_L2: l2-cache1 {
compatible = "cache";
+ cache-unified;
cache-size = <0x100000>;
cache-line-size = <64>;
cache-sets = <1024>;
diff --git a/arch/arm64/boot/dts/arm/rtsm_ve-aemv8a.dts b/arch/arm64/boot/dts/arm/rtsm_ve-aemv8a.dts
index 258991ad7cc0..ef68f5aae7dd 100644
--- a/arch/arm64/boot/dts/arm/rtsm_ve-aemv8a.dts
+++ b/arch/arm64/boot/dts/arm/rtsm_ve-aemv8a.dts
@@ -71,6 +71,7 @@ cpu@3 {
L2_0: l2-cache0 {
compatible = "cache";
+ cache-level = <2>;
};
};
diff --git a/arch/arm64/boot/dts/arm/vexpress-v2f-1xv7-ca53x2.dts b/arch/arm64/boot/dts/arm/vexpress-v2f-1xv7-ca53x2.dts
index 5b6d9d8e934d..796cd7d02eb5 100644
--- a/arch/arm64/boot/dts/arm/vexpress-v2f-1xv7-ca53x2.dts
+++ b/arch/arm64/boot/dts/arm/vexpress-v2f-1xv7-ca53x2.dts
@@ -57,6 +57,7 @@ cpu@1 {
L2_0: l2-cache0 {
compatible = "cache";
+ cache-level = <2>;
};
};
meta-arm/meta-arm-bsp/recipes-kernel/linux/files/juno/0002-arm64-dts-fvp-Add-SPE-to-Foundation-FVP.patch
+35
View File
@@ -0,0 +1,35 @@
From bd354219987dddbf8ab6fd11450b4046547aca1b Mon Sep 17 00:00:00 2001
From: James Clark <james.clark@arm.com>
Date: Thu, 17 Nov 2022 10:25:36 +0000
Subject: [PATCH] arm64: dts: fvp: Add SPE to Foundation FVP
Add SPE DT node to FVP model. If the model doesn't support SPE (e.g.,
turned off via parameter), the driver will skip the initialisation
accordingly and thus is safe.
Signed-off-by: James Clark <james.clark@arm.com>
Link: https://lore.kernel.org/r/20221117102536.237515-1-james.clark@arm.com
Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
Signed-off-by: Jon Mason <jon.mason@arm.com>
Upstream-Status: Backport
---
arch/arm64/boot/dts/arm/foundation-v8.dtsi | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/arch/arm64/boot/dts/arm/foundation-v8.dtsi b/arch/arm64/boot/dts/arm/foundation-v8.dtsi
index c8bd23b1a7ba..029578072d8f 100644
--- a/arch/arm64/boot/dts/arm/foundation-v8.dtsi
+++ b/arch/arm64/boot/dts/arm/foundation-v8.dtsi
@@ -85,6 +85,11 @@ pmu {
<GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
};
+ spe-pmu {
+ compatible = "arm,statistical-profiling-extension-v1";
+ interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
watchdog@2a440000 {
compatible = "arm,sbsa-gwdt";
reg = <0x0 0x2a440000 0 0x1000>,
meta-arm/meta-arm-bsp/recipes-kernel/linux/files/juno/0003-arm64-dts-fvp-Add-information-about-L1-and-L2-caches.patch
+146
View File
@@ -0,0 +1,146 @@
From 22e740d069e14875a64864bf86e0826a96560b44 Mon Sep 17 00:00:00 2001
From: Sudeep Holla <sudeep.holla@arm.com>
Date: Fri, 18 Nov 2022 15:10:17 +0000
Subject: [PATCH] arm64: dts: fvp: Add information about L1 and L2 caches
Add the information about L1 and L2 caches on FVP RevC platform.
Though the cache size is configurable through the model parameters,
having default values in the device tree helps to exercise and debug
any code utilising the cache information without the need of real
hardware.
Link: https://lore.kernel.org/r/20221118151017.704716-1-sudeep.holla@arm.com
Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
Signed-off-by: Jon Mason <jon.mason@arm.com>
Upstream-Status: Backport
---
arch/arm64/boot/dts/arm/fvp-base-revc.dts | 73 +++++++++++++++++++++++
1 file changed, 73 insertions(+)
diff --git a/arch/arm64/boot/dts/arm/fvp-base-revc.dts b/arch/arm64/boot/dts/arm/fvp-base-revc.dts
index 5f6f30c801a7..60472d65a355 100644
--- a/arch/arm64/boot/dts/arm/fvp-base-revc.dts
+++ b/arch/arm64/boot/dts/arm/fvp-base-revc.dts
@@ -47,48 +47,121 @@ cpu0: cpu@0 {
compatible = "arm,armv8";
reg = <0x0 0x000>;
enable-method = "psci";
+ i-cache-size = <0x8000>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <0x8000>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <256>;
+ next-level-cache = <&C0_L2>;
};
cpu1: cpu@100 {
device_type = "cpu";
compatible = "arm,armv8";
reg = <0x0 0x100>;
enable-method = "psci";
+ i-cache-size = <0x8000>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <0x8000>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <256>;
+ next-level-cache = <&C0_L2>;
};
cpu2: cpu@200 {
device_type = "cpu";
compatible = "arm,armv8";
reg = <0x0 0x200>;
enable-method = "psci";
+ i-cache-size = <0x8000>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <0x8000>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <256>;
+ next-level-cache = <&C0_L2>;
};
cpu3: cpu@300 {
device_type = "cpu";
compatible = "arm,armv8";
reg = <0x0 0x300>;
enable-method = "psci";
+ i-cache-size = <0x8000>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <0x8000>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <256>;
+ next-level-cache = <&C0_L2>;
};
cpu4: cpu@10000 {
device_type = "cpu";
compatible = "arm,armv8";
reg = <0x0 0x10000>;
enable-method = "psci";
+ i-cache-size = <0x8000>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <0x8000>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <256>;
+ next-level-cache = <&C1_L2>;
};
cpu5: cpu@10100 {
device_type = "cpu";
compatible = "arm,armv8";
reg = <0x0 0x10100>;
enable-method = "psci";
+ i-cache-size = <0x8000>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <0x8000>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <256>;
+ next-level-cache = <&C1_L2>;
};
cpu6: cpu@10200 {
device_type = "cpu";
compatible = "arm,armv8";
reg = <0x0 0x10200>;
enable-method = "psci";
+ i-cache-size = <0x8000>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <0x8000>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <256>;
+ next-level-cache = <&C1_L2>;
};
cpu7: cpu@10300 {
device_type = "cpu";
compatible = "arm,armv8";
reg = <0x0 0x10300>;
enable-method = "psci";
+ i-cache-size = <0x8000>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <0x8000>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <256>;
+ next-level-cache = <&C1_L2>;
+ };
+ C0_L2: l2-cache0 {
+ compatible = "cache";
+ cache-size = <0x80000>;
+ cache-line-size = <64>;
+ cache-sets = <512>;
+ cache-level = <2>;
+ cache-unified;
+ };
+
+ C1_L2: l2-cache1 {
+ compatible = "cache";
+ cache-size = <0x80000>;
+ cache-line-size = <64>;
+ cache-sets = <512>;
+ cache-level = <2>;
+ cache-unified;
};
};
meta-arm/meta-arm-bsp/recipes-kernel/linux/files/juno/0004-ARM-dts-vexpress-align-LED-node-names-with-dtschema.patch
+81
View File
@@ -0,0 +1,81 @@
From 4edb625e2256d5761312110e34cbc0164915d772 Mon Sep 17 00:00:00 2001
From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Date: Fri, 25 Nov 2022 15:41:12 +0100
Subject: [PATCH] ARM: dts: vexpress: align LED node names with dtschema
The node names should be generic and DT schema expects certain pattern.
vexpress-v2p-ca9.dtb: leds: 'user1', 'user2', 'user3', 'user4', 'user5', 'user6', 'user7', 'user8' do not match any of the regexes: '(^led-[0-9a-f]$|led)', 'pinctrl-[0-9]+'
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20221125144112.476817-1-krzysztof.kozlowski@linaro.org
Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
Signed-off-by: Jon Mason <jon.mason@arm.com>
Upstream-Status: Backport
---
arch/arm/boot/dts/vexpress-v2m.dtsi | 16 ++++++++--------
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/arch/arm/boot/dts/vexpress-v2m.dtsi b/arch/arm/boot/dts/vexpress-v2m.dtsi
index f434fe5cf4a1..def538ce8769 100644
--- a/arch/arm/boot/dts/vexpress-v2m.dtsi
+++ b/arch/arm/boot/dts/vexpress-v2m.dtsi
@@ -383,49 +383,49 @@ v2m_refclk32khz: refclk32khz {
leds {
compatible = "gpio-leds";
- user1 {
+ led-user1 {
label = "v2m:green:user1";
gpios = <&v2m_led_gpios 0 0>;
linux,default-trigger = "heartbeat";
};
- user2 {
+ led-user2 {
label = "v2m:green:user2";
gpios = <&v2m_led_gpios 1 0>;
linux,default-trigger = "mmc0";
};
- user3 {
+ led-user3 {
label = "v2m:green:user3";
gpios = <&v2m_led_gpios 2 0>;
linux,default-trigger = "cpu0";
};
- user4 {
+ led-user4 {
label = "v2m:green:user4";
gpios = <&v2m_led_gpios 3 0>;
linux,default-trigger = "cpu1";
};
- user5 {
+ led-user5 {
label = "v2m:green:user5";
gpios = <&v2m_led_gpios 4 0>;
linux,default-trigger = "cpu2";
};
- user6 {
+ led-user6 {
label = "v2m:green:user6";
gpios = <&v2m_led_gpios 5 0>;
linux,default-trigger = "cpu3";
};
- user7 {
+ led-user7 {
label = "v2m:green:user7";
gpios = <&v2m_led_gpios 6 0>;
linux,default-trigger = "cpu4";
};
- user8 {
+ led-user8 {
label = "v2m:green:user8";
gpios = <&v2m_led_gpios 7 0>;
linux,default-trigger = "cpu5";