49 lines
1.6 KiB
Diff
49 lines
1.6 KiB
Diff
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From 521c121eccb386aca7c75d92528e495546adccec Mon Sep 17 00:00:00 2001
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From: Jaxson Han <jaxson.han@arm.com>
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Date: Mon, 25 Oct 2021 17:09:13 +0800
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Subject: [PATCH] aarch64: Disable CNTPCT_EL0 trap for v8-R64
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To allow EL1 to access CNTPCT_EL0 without traping into EL2, we need to
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set CNTHCTL_EL2.EL1PCTEN to 1.
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For v8-R64, the CNTHCTL_EL2 register follows the v8-A architecture.
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However, as described in the v8-A architecture profile, the
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CNTHCTL_EL2's bit assignments are different according to whether the
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FEAT_VHE is implemented.
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Since v8-R64 does not support FEAT_VHE, we do not need to detect
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FEAT_VHE. We can simply set CNTHCTL_EL2.EL1PCTEN to 1.
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Issue-ID: SCM-3508
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Upstream-Status: Inappropriate [other]
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Implementation pending further discussion
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Signed-off-by: Jaxson Han <jaxson.han@arm.com>
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Change-Id: I4147e66341c8153312021e6f2ab67d0037246da1
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---
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arch/aarch64/boot.S | 12 ++++++++++++
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1 file changed, 12 insertions(+)
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diff --git a/arch/aarch64/boot.S b/arch/aarch64/boot.S
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index a219ea7..27b1139 100644
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--- a/arch/aarch64/boot.S
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+++ b/arch/aarch64/boot.S
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@@ -240,6 +240,18 @@ el2_init:
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orr x0, x0, #(1 << 41) // HCR_EL2.API
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1: msr hcr_el2, x0
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+
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+ /*
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+ * To disable trap when accessing CNTPCT_EL0, we need to set
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+ * CNTHCTL_EL2.EL1PCTEN to 1. However, the CNTHCTL_EL2 bit assignments
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+ * are different according to whether the FEAT_VHE is implemented.
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+ *
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+ * For Armv8-R AArch64, FEAT_VHE is not supported, so we do not need to
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+ * detect FEAT_VHE(ID_AA64MMFR1_EL1.VH) and simply set
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+ * CNTHCTL_EL2.EL1PCTEN to 1.
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+ */
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+ mov x0, #1 // CNTHCTL_EL2.EL1PCTEN
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+ msr cnthctl_el2, x0
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isb
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mov w0, #SPSR_KERNEL_EL1
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