106 lines
3.4 KiB
Diff
106 lines
3.4 KiB
Diff
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From bff110a95a5e4c9db2d61e629b4aa4b84530201e Mon Sep 17 00:00:00 2001
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From: Jaxson Han <jaxson.han@arm.com>
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Date: Tue, 25 May 2021 07:25:00 +0100
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Subject: [PATCH] gic-v3: Prepare for gicv3 with EL2
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This is a preparation for allowing boot-wrapper configuring the gicv3
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with EL2.
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When confiuring with EL2, since there is no ICC_CTLR_EL2, the
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ICC_CTLR_EL3 cannot be replaced with ICC_CTLR_EL2 simply.
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See [https://developer.arm.com/documentation/ihi0069/latest/].
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As the caller, gic_secure_init expects the ICC_CTLR to be written,
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we change the function into gic_init_icc_ctlr(). In the GIC spec,
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the r/w bits in this register ([6:0]) either affect EL3 IRQ routing
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(not applicable since no EL3), non-secure IRQ handling (not applicable
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since only secure state in Armv8-R aarch64), or are aliased to
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ICC_CTLR_EL1 bits.
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So, based on this, the new gic_init_icc_ctlr() would be:
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When currentEL is EL3, init ICC_CTLR_EL3 as before.
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When currentEL is not EL3, init ICC_CTLR_EL1 with ICC_CTLR_EL1_RESET.
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Upstream-Status: Pending
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Signed-off-by: Jaxson Han <jaxson.han@arm.com>
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Reviewed-by: Andre Przywara <andre.przywara@arm.com>
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---
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arch/aarch32/include/asm/gic-v3.h | 7 +++++++
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arch/aarch64/include/asm/gic-v3.h | 23 ++++++++++++++++++++---
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common/gic-v3.c | 2 +-
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3 files changed, 28 insertions(+), 4 deletions(-)
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diff --git a/arch/aarch32/include/asm/gic-v3.h b/arch/aarch32/include/asm/gic-v3.h
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index 65f38de..11e7bc7 100644
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--- a/arch/aarch32/include/asm/gic-v3.h
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+++ b/arch/aarch32/include/asm/gic-v3.h
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@@ -9,6 +9,8 @@
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#ifndef __ASM_AARCH32_GICV3_H
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#define __ASM_AARCH32_GICV3_H
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+#define ICC_CTLR_RESET (0UL)
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+
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static inline void gic_write_icc_sre(uint32_t val)
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{
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asm volatile ("mcr p15, 6, %0, c12, c12, 5" : : "r" (val));
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@@ -19,4 +21,9 @@ static inline void gic_write_icc_ctlr(uint32_t val)
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asm volatile ("mcr p15, 6, %0, c12, c12, 4" : : "r" (val));
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}
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+static inline void gic_init_icc_ctlr()
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+{
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+ gic_write_icc_ctlr(ICC_CTLR_RESET);
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+}
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+
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#endif
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diff --git a/arch/aarch64/include/asm/gic-v3.h b/arch/aarch64/include/asm/gic-v3.h
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index 5b32380..090ab0b 100644
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--- a/arch/aarch64/include/asm/gic-v3.h
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+++ b/arch/aarch64/include/asm/gic-v3.h
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@@ -15,14 +15,31 @@
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#define ICC_CTLR_EL3 "S3_6_C12_C12_4"
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#define ICC_PMR_EL1 "S3_0_C4_C6_0"
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+#define ICC_CTLR_EL3_RESET (0UL)
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+#define ICC_CTLR_EL1_RESET (0UL)
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+
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+static inline uint32_t current_el(void)
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+{
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+ uint32_t val;
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+
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+ asm volatile ("mrs %0, CurrentEL" : "=r" (val));
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+ return val;
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+}
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+
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static inline void gic_write_icc_sre(uint32_t val)
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{
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- asm volatile ("msr " ICC_SRE_EL3 ", %0" : : "r" (val));
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+ if (current_el() == CURRENTEL_EL3)
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+ asm volatile ("msr " ICC_SRE_EL3 ", %0" : : "r" (val));
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+ else
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+ asm volatile ("msr " ICC_SRE_EL2 ", %0" : : "r" (val));
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}
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-static inline void gic_write_icc_ctlr(uint32_t val)
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+static inline void gic_init_icc_ctlr()
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{
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- asm volatile ("msr " ICC_CTLR_EL3 ", %0" : : "r" (val));
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+ if (current_el() == CURRENTEL_EL3)
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+ asm volatile ("msr " ICC_CTLR_EL3 ", %0" : : "r" (ICC_CTLR_EL3_RESET));
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+ else
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+ asm volatile ("msr " ICC_CTLR_EL1 ", %0" : : "r" (ICC_CTLR_EL1_RESET));
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}
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#endif
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diff --git a/common/gic-v3.c b/common/gic-v3.c
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index 6207007..a0fe564 100644
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--- a/common/gic-v3.c
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+++ b/common/gic-v3.c
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@@ -117,6 +117,6 @@ void gic_secure_init(void)
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gic_write_icc_sre(ICC_SRE_Enable | ICC_SRE_DIB | ICC_SRE_DFB | ICC_SRE_SRE);
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isb();
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- gic_write_icc_ctlr(0);
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+ gic_init_icc_ctlr();
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isb();
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}
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